PIC16F87 datasheet(76/230 Pages) MICROCHIP

76 / 230 page

PIC16F87/88

DS30487D-page 76

 2002-2013 Microchip Technology Inc.

7.8

Resetting Timer1 Using a CCP

Trigger Output

If the CCP1 module is configured in Compare mode to

generate

“special

event

trigger”

signal

(CCP1M3:CCP1M0 = 1011), the signal will reset

Timer1 and start an A/D conversion (if the A/D module

is enabled).

Timer1 must be configured for either Timer or Synchro-

nized Counter mode to take advantage of this feature.

If Timer1 is running in Asynchronous Counter mode,

this Reset operation may not work.

In the event that a write to Timer1 coincides with a

special event trigger from CCP1, the write will take

precedence.

In this mode of operation, the CCPR1H:CCPR1L

Timer1.

7.9

Resetting Timer1 Register Pair

(TMR1H, TMR1L)

TMR1H and TMR1L registers are not reset to 00h on a

POR, or any other Reset, except by the CCP1 special

event triggers.

T1CON register is reset to 00h on a Power-on Reset or

a Brown-out Reset, which shuts off the timer and

leaves a 1:1 prescale. In all other Resets, the register

is unaffected.

7.10

Timer1 Prescaler

The prescaler counter is cleared on writes to the

TMR1H or TMR1L registers.

7.11

Using Timer1 as a Real-Time

Clock

Adding an external LP oscillator to Timer1 (such as the

one described in Section 7.6 “Timer1 Oscillator”)

gives users the option to include RTC functionality to

their applications. This is accomplished with an inex-

pensive watch crystal to provide an accurate time base

and several lines of application code to calculate the

time. When operating in Sleep mode and using a

battery or supercapacitor as a power source, it can

completely eliminate the need for a separate RTC

device and battery backup.

The application code routine, RTCisr, shown in

Example 7-3, demonstrates a simple method to

increment a counter at one-second intervals using an

Interrupt Service Routine. Incrementing the TMR1

the routine, which increments the seconds counter by

one; additional counters for minutes and hours are

incremented as the previous counter overflows.

Since the register pair is 16 bits wide, counting up to

overflow the register directly from a 32.768 kHz clock

would take 2 seconds. To force the overflow at the

required one-second intervals, it is necessary to pre-

load it; the simplest method is to set the MSb of TMR1H

with a BSF instruction. Note that the TMR1L register is

never preloaded or altered; doing so may introduce

cumulative error over many cycles.

For this method to be accurate, Timer1 must operate in

Asynchronous mode and the Timer1 overflow interrupt

must be enabled (PIE1<0> = 1), as shown in the

routine, RTCinit. The Timer1 oscillator must also be

enabled and running at all times.

Note:

The special event triggers from the CCP1

module will not set interrupt flag bit,

TMR1IF (PIR1<0>).

PIC16F87 датащи(PDF) 76 Page - Microchip Technology

PIC16F87 датащи(HTML) 76 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL