PIC16F87 datasheet(67/230 Pages) MICROCHIP

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 2002-2013 Microchip Technology Inc.

DS30487D-page 67

PIC16F87/88

6.0

TIMER0 MODULE

The Timer0 module timer/counter has the following

features:

• 8-bit timer/counter

• Readable and writable

• 8-bit software programmable prescaler

• Internal or external clock select

• Interrupt-on-overflow from FFh to 00h

• Edge select for external clock

Additional information on the Timer0 module is

available in the “PIC® Mid-Range MCU Family Refer-

ence Manual” (DS33023).

Figure 6-1 is a block diagram of the Timer0 module and

the prescaler shared with the WDT.

6.1

Timer0 Operation

Timer0

operation

controlled

through

the

OPTION_REG register (see Register 2-2). Timer mode

is selected by clearing bit T0CS (OPTION_REG<5>).

In Timer mode, the Timer0 module will increment every

instruction cycle (without prescaler). If the TMR0 regis-

ter is written, the increment is inhibited for the following

two instruction cycles. The user can work around this

by writing an adjusted value to the TMR0 register.

Counter mode is selected by setting bit T0CS

(OPTION_REG<5>). In Counter mode, Timer0 will incre-

ment, either on every rising or falling edge of pin RA4/

T0CKI/C2OUT. The incrementing edge is determined by

the

Timer0

Source

Edge

Select

bit,

T0SE

(OPTION_REG<4>). Clearing bit T0SE selects the rising

edge. Restrictions on the external clock input are

discussed in detail in Section 6.3 “Using Timer0 with

an External Clock”.

The prescaler is mutually, exclusively shared between

the Timer0 module and the Watchdog Timer. The

prescaler is not readable or writable. Section 6.4

“Prescaler” details the operation of the prescaler.

6.2

Timer0 Interrupt

The TMR0 interrupt is generated when the TMR0 reg-

ister overflows from FFh to 00h. This overflow sets bit

TMR0IF (INTCON<2>). The interrupt can be masked

by clearing bit TMR0IE (INTCON<5>). Bit TMR0IF

must be cleared in software by the Timer0 module

Interrupt Service Routine before re-enabling this inter-

rupt. The TMR0 interrupt cannot awaken the processor

from Sleep, since the timer is shut off during Sleep.

FIGURE 6-1:

BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

RA4/T0CKI/C2OUT

T0SE

CLKO (= FOSC/4)

Sync

Cycles

TMR0 reg

8-bit Prescaler

8-to-1 MUX

M U X

PSA

WDT

Time-out

PS2:PS0

Note: T0CS, T0SE, PSA and PS2:PS0 bits are (OPTION_REG<5:0>).

PSA

Data Bus

Set Flag bit TMR0IF

on Overflow

PSA

T0CS

Prescaler

31.25 kHz

WDT Timer

WDT Enable bit

16-bit

Prescaler

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