PIC16F87 datasheet(93/230 Pages) MICROCHIP

93 / 230 page

 2002-2013 Microchip Technology Inc.

DS30487D-page 93

PIC16F87/88

10.3.1

SLAVE MODE

In Slave mode, the SCL and SDA pins must be config-

ured as inputs (TRISB<4,1> set). The SSP module will

override the input state with the output data when

required (slave-transmitter).

When an address is matched, or the data transfer after

an address match is received, the hardware automati-

cally will generate the Acknowledge (ACK) pulse and

then load the SSPBUF register with the received value

currently in the SSPSR register.

Either or both of the following conditions will cause the

SSP module not to give this ACK pulse:

The Buffer Full bit, BF (SSPSTAT<0>), was set

before the transfer was received.

The Overflow bit, SSPOV (SSPCON<6>), was

set before the transfer was received.

In this case, the SSPSR register value is not loaded

into the SSPBUF, but bit SSPIF (PIR1<3>) is set.

Table 10-2 shows what happens when a data transfer

byte is received, given the status of bits BF and

SSPOV. The shaded cells show the condition where

user software did not properly clear the overflow condi-

tion. Flag bit, BF, is cleared by reading the SSPBUF

The SCL clock input must have a minimum high and

low for proper operation. The high and low times of the

I2C specification, as well as the requirement of the SSP

module, are shown in timing parameter #100 and

parameter #101.

10.3.1.1

Addressing

Once the SSP module has been enabled, it waits for a

Start condition to occur. Following the Start condition,

the eight bits are shifted into the SSPSR register. All

incoming bits are sampled with the rising edge of the

clock (SCL) line. The value of register SSPSR<7:1> is

compared to the value of the SSPADD register. The

address is compared on the falling edge of the eighth

clock (SCL) pulse. If the addresses match and the BF

and SSPOV bits are clear, the following events occur:

The SSPSR register value is loaded into the

SSPBUF register.

The Buffer Full bit, BF, is set.

An ACK pulse is generated.

SSP Interrupt Flag bit, SSPIF (PIR1<3>), is set

(interrupt is generated if enabled) – on the falling

edge of the ninth SCL pulse.

In 10-bit Address mode, two address bytes need to be

received by the slave device. The five Most Significant

bits (MSbs) of the first address byte specify if this is a

10-bit address. Bit R/W (SSPSTAT<2>) must specify a

write so the slave device will receive the second

address byte. For a 10-bit address, the first byte would

equal ‘1111 0 A9 A8 0’, where A9 and A8 are the

two MSbs of the address.

The sequence of events for 10-bit Address mode is as

follows, with steps 7-9 for slave transmitter:

Receive first (high) byte of address (bits SSPIF,

BF and UA (SSPSTAT<1>) are set).

Update the SSPADD register with second (low)

byte of address (clears bit UA and releases the

SCL line).

Read the SSPBUF register (clears bit BF) and

clear flag bit SSPIF.

Receive second (low) byte of address (bits

SSPIF, BF and UA are set).

Update the SSPADD register with the first (high)

byte of address; if match releases SCL line, this

will clear bit UA.

Read the SSPBUF register (clears bit BF) and

clear flag bit SSPIF.

Receive Repeated Start condition.

Receive first (high) byte of address (bits SSPIF

and BF are set).

Read the SSPBUF register (clears bit BF) and

clear flag bit SSPIF.

10.3.1.2

Reception

When the R/W bit of the address byte is clear and an

address match occurs, the R/W bit of the SSPSTAT

the SSPBUF register.

When the address byte overflow condition exists, then

a no Acknowledge (ACK) pulse is given. An overflow

condition is indicated if either bit, BF (SSPSTAT<0>), is

set or bit, SSPOV (SSPCON<6>), is set.

An SSP interrupt is generated for each data transfer

byte. Flag bit, SSPIF (PIR1<3>), must be cleared in

software. The SSPSTAT register is used to determine

the status of the byte.

10.3.1.3

Transmission

When the R/W bit of the incoming address byte is set

and an address match occurs, the R/W bit of the

SSPSTAT register is set. The received address is

loaded into the SSPBUF register. The ACK pulse will

be sent on the ninth bit and pin RB4/SCK/SCL is held

low. The transmit data must be loaded into the

SSPBUF register which also loads the SSPSR register.

Then, pin RB4/SCK/SCL should be enabled by setting

bit CKP (SSPCON<4>). The master device must mon-

itor the SCL pin prior to asserting another clock pulse.

The slave devices may be holding off the master device

by stretching the clock. The eight data bits are shifted

out on the falling edge of the SCL input. This ensures

that the SDA signal is valid during the SCL high time

(Figure 10-7).

PIC16F87 датащи(PDF) 93 Page - Microchip Technology

PIC16F87 датащи(HTML) 93 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL