AD9508PCBZ datasheet(23/40 Pages) AD

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Data Sheet

AD9508

Rev. A | Page 23 of 40

CLOCK DIVIDERS

The four independent channel dividers are 10-bit integer

dividers with a divide range of 1 to 1024 in SPI and I2C modes.

The channel divider block contains duty cycle correction that

guarantees 50% duty cycle for both even and odd divide ratios.

In pin programming mode, divide values of 1 to 8 and 16 are

supported.

PHASE DELAY CONTROL

The AD9508 provides a coarse output phase delay adjustment

between outputs but with a wide delay range that is beneficial

for some applications. The minimum delay step is equivalent to

half the period of the input clock rate. This minimum delay step

can be multiplied from 1 to 2047 times the minimum delay step

to cover a wide delay range. The multiplication of the minimum

delay step is provided for each channel output via the appropriate

internal programming register. Phase delay is not supported in

pin programming mode.

Note that the phase delay adjustment requires the use of the

SYNC function pin. Phase adjustment and output synchroni-

zation occurs on the rising edge of the SYNC pin. Therefore, the

SYNC pin must be pulled low and released to produce the

desired phase relationship between outputs. If the SYNC is not

active low prior to a phase delay change, the desired output

phase delay between outputs is not guaranteed to occur;

instead, a random phase delay can occur between outputs.

However, a future SYNC pulse corrects to the desired phase

relationship, if initiated. During the active low SYNC period,

the outputs are forced to a static state.

Figure 46 shows three independent outputs, each set for DIV = 4

of the input clock rate. By incrementing the phase offset value

in the programming registers from 0 to 2, each output is offset

from the initial edge by a multiple of ½ tCLK. Note that the SYNC

signal is not shown in this timing diagram.

Figure 46. Phase Offset—All Dividers Set for DIV = 4, Phase Set from 0 to 2

RESET MODES

The AD9508 has a power-on reset (POR) and other ways to

apply a reset condition to the chip.

Power-On Reset

During chip power-up, an internal power-on reset pulse is

issued when VDD reaches ~1.15 V and restores the chip to the

default on-chip setting. It takes ~20 ms for the outputs to begin

toggling after the power-on reset pulse signal is internally

generated.

In SPI or I2C modes, the default power-on state of the AD9508

is configured as a buffer with the dividers set to divide by 1. In

pin programmable mode, the part is configured per the

hardwiring of the S0 to S5 pins.

Hardware Reset via the RESET Pin

A hard asynchronous reset is executed by briefly pulling RESET

low. This restores the chip to the on-chip default register settings.

It takes ~20 ms for the outputs to begin toggling after RESET is

released.

Soft Reset via the Serial Port

A soft reset is initiated by setting Bit 2 and Bit 5 in Register 0x000.

Except for Register 0x000, when Bit 5 and Bit 2 are set, the chip

enters a soft reset mode and restores the chip to the on-chip

setting. These bits are self clearing. However, the self clearing

operation does not complete until an additional serial port SCLK

cycle occurs, and the AD9508 is held in reset until that happens.

POWER-DOWN MODE

Individual Clock Channel Power-Down

In SPI or I²C programming mode, the clock distribution

channels can be powered down individually by writing to the

appropriate registers. Powering down a clock channel is similar

to powering down an individual driver, but it saves more power

because additional circuits are also powered down. The register

map details the individual power-down settings for each output

channel. These settings are found in Register 0x0F0, Bit 4; Regis-

ter 0x0F2, Bit 4; Register 0x0F4, Bit 4; and Register 0x0F6, Bit 4.

Note that in all three programming modes, a logic low on the

RESET pin can be used to power down the device.

9 10

11 12 13 14 15

CLOCK INPUT

CLK

DIVIDER OUTPUTS

DIV = 4, DUTY = 50%

START = 0,

PHASE = 0

START = 0,

PHASE = 1

START = 0,

PHASE = 2

tCLK

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