AD9508PCBZ datasheet(35/40 Pages) AD

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Data Sheet

AD9508

Rev. A | Page 35 of 40

OUT1 FUNCTIONS (REGISTER 0x1B TO REGISTER 0x20)

Table 29. Divide Ratio and Phase

Address

Bits

Bit Name

Description

0x1B

[7:0]

OUT1 Divide Ratio[7:0]

Channel 1 divide ratio, Bits[7:0]

0x1C

[7:2]

Reserved

0x00 = default

[1:0]

OUT1 Divide Ratio[9:8]

Channel 1 divide ratio, Bits[9:8]

0x1D

[7:0]

OUT1 Phase[7:0]

Channel 1 divider phase, Bits[7:0]

0x1E

[7:3]

Reserved

0x00 = default

[2:0]

OUT1 Phase[10:8]

Channel 1 divider phase, Bits[9:8]

Table 30. Output Driver, Power Down, and Sync

Address

Bits

Bit Name

Description

0x1F

PD_1

Channel 1 power-down

SYNCMASK1

Setting this bit masks Channel 1 from the output sync function

0 = Channel 1 is synchronized during output sync (default)

1 = Channel 1 is excluded from an output sync

[5:4]

OUT1 Driver Phase[1:0]

These bits determine the phase of the OUT1 driver

00 = force high

01 = noninverting (default)

10 = inverting

11 = force low

[3:1]

OUT1 Mode[2:0]

These bits determine the OUT1 driver mode

000 = LVDS 0.5 × 3.5 mA (1/2 amplitude)

001 = LVDS 0.75 × 3.5 mA (3/4 amplitude)

010 = LVDS 1 × 3.5 mA (default)

011 = LVDS 1.25 × 3.5 mA (1.25 amplitude)

100 = HSTL 1 × 3.5 mA (normal amplitude)

101 = HSTL 2 × 3.5 mA (double amplitude)

110 = high-Z/CMOS

111 = high-Z/CMOS

Reserved

0b = default

0x20

EN_CMOS_1P

Setting this bit enables the OUT1P CMOS driver

0 = disables the OUT1P CMOS driver (default)

1 = enables the OUT1P CMOS driver

[6:5]

CMOS_1P_PHASE[1:0]

These bits determine the phase of the OUT1P CMOS driver

00 = force high (default)

01 = noninverting

10 = inverting

11 = force low

[4]

EN_CMOS_1N

Setting this bit enables the OUT1N CMOS driver

0 = disables the OUT1N CMOS driver (default)

1 = enables the OUT1N CMOS driver

[3:2]

CMOS_1N_PHASE[1:0]

These bits determine the phase of the OUT1N CMOS driver

00 = force high (default)

01 = noninverting

10 = inverting

11 = force low

[1:0]

Reserved

00b = default

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