Data Sheet

AD9508

Rev. A | Page 31 of 40

Figure 58. Data Transfer Process (Master Read Mode, Two-Byte Transfer)

Data Transfer Format

Write byte format: The write byte protocol writes a register address to the RAM, starting from the specified RAM address.

S

Slave

Address

A

A

RAM Address

High Byte

A

RAM Address

Low Byte

A

RAM

Data 0

A

RAM

Data 1

A

RAM

Data 2

A

P

Send byte format: The send byte protocol sets up the register address for subsequent reads.

S

Slave Address

A

A

RAM Address High Byte

A

RAM Address Low Byte

A

P

Receive byte format: The receive byte protocol reads the data byte(s) from RAM, starting from the current address.

S

Slave Address

R

A

RAM Data 0

A

RAM Data 1

A

RAM Data 2

A

A

E

P

Read byte format: This is the combined format of the send byte and the receive byte.

S

Slave

Address

A

A

RAM

Address

High Byte

A

RAM

Address

Low Byte

A

Sr

Slave

Address

R

A

RAM

Data 0

A

RAM

Data 1

A

RAM

Data 2

A

A

E

P

I²C Serial Port Timing

Figure 59. I²C Serial Port Timing

Table 22. I2C Timing Definitions

Parameter

Description

Serial clock

Bus free time between stop and start conditions

Repeated hold time start condition

Repeated start condition setup time

Stop condition setup time

Data hold time

Date setup time

SCL clock low period

SCL clock high period

Minimum/maximum receive SCL and SDA rise time

Minimum/maximum receive SCL and SDA fall time

Pulse width of voltage spikes that must be suppressed by the input filter

12

89

12

3TO 7

3TO 7

89

10

ACK FROM

MASTER RECEIVER

NACK FROM

MASTER RECEIVER

SDA

SCL

S

P

SSr

S

P

SDA

SCL