AD9508PCBZ datasheet(36/40 Pages) AD

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AD9508

Data Sheet

Rev. A | Page 36 of 40

OUT2 FUNCTIONS (REGISTER 0x21 TO REGISTER 0x26)

Table 31. Divide Ratio and Phase

Address

Bits

Bit Name

Description

0x21

[7:0]

OUT2 Divide Ratio[7:0]

Channel 2 divide ratio, Bits[7:0]

0x22

[7:2]

Reserved

0x00 = default

[1:0]

OUT2 Divide Ratio[9:8]

Channel 2 divide ratio, Bits[9:8]

0x23

[7:0]

OUT2 Phase[7:0]

Channel 2 divider phase, Bits[7:0]

0x24

[7:3]

Reserved

0x00 = default

[2:0]

OUT2 Phase[10:8]

Channel 2 divider phase, Bits[9:8]

Table 32. Output Driver, Power Down, and Sync

Address

Bits

Bit Name

Description

0x25

PD_2

Channel 2 power-down

SYNCMASK2

Setting this bit masks OUT2 from the output sync function

0 = Channel 2 is synchronized during output sync (default)

1 = Channel 2 is excluded from an output sync

[5:4]

OUT2 Driver Phase[1:0]

These bits determine the phase of the OUT2 driver

00 = force high

01 = noninverting (default)

10 = inverting

11 = force low

[3:1]

OUT2 Mode[2:0]

These bits determine the OUT2 driver mode

000 = LVDS 0.5 × 3.5 mA (1/2 amplitude)

001 = LVDS 0.75 × 3.5 mA (3/4 amplitude)

010 = LVDS 1 × 3.5 mA (default)

011 = LVDS 1.25 × 3.5 mA (1.25 amplitude)

100 = HSTL 1 × 3.5 mA (normal amplitude)

101 = HSTL 2 × 3.5 mA (double amplitude)

110 = high-Z/CMOS

111 = high-Z/CMOS

Reserved

0b = default

0x26

EN_CMOS_2P

Setting this bit enables the OUT2P CMOS driver

0 = disables the OUT2P CMOS driver (default)

1 = enables OUT2P CMOS driver

[6:5]

CMOS_2P_PHASE[1:0]

These bits determine the phase of the OUT2P CMOS driver

00 = force high (default)

01 = noninverting

10 = inverting

11 = force low

EN_CMOS_2N

Setting this bit enables the OUT2N CMOS driver

0 = disables the OUT2N CMOS driver (default)

1 = enables OUT2N CMOS driver

[3:2]

CMOS_2N_PHASE[1:0]

These bits determine the phase of the OUT2N CMOS driver

00 = force high (default)

01 = noninverting

10 = inverting

11 = force low

[1:0]

Reserved

00b = default

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