AD9508PCBZ datasheet(16/40 Pages) AD

номер детали	AD9508PCBZ

подробное описание детали	1.65 GHz Clock Fanout Buffer with Output Dividers and Delay Adjust

PDF	40 Pages

Scroll/Zoom	100%

производитель	AD [Analog Devices]

домашняя страница	http://www.analog.com

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16 / 40 page

AD9508

Data Sheet

Rev. A | Page 16 of 40

Figure 21. HSTL Differential Output Swing vs. Power Supply Voltage

Figure 22. HSTL Propagation Delay vs. Input Differential Voltage

Figure 23. HSTL Propagation Delay vs. Input Common-Mode Voltage

Figure 24. HSTL Output Duty Cycle vs. Output Frequency

Figure 25. Additive Broadband Jitter vs. Input Slew Rate, LVDS, HSTL

(Calculated from SNR of ADC Method)

Figure 26. Absolute Phase Noise in HSTL Mode with Clock Input @

622.08 MHz and Outputs = 622.08 MHz, 311.04 MHz, 155.52 MHz

2.0

POWER SUPPLY (V)

2.3

2.5

3.1

2.9

2.7

3.3

3.5

1.9

1.8

1.7

1.6

1.5

2.0

2.1

2.2

2.3

2.4

1.8

1.7

2.0

1.6

1.8

1.4

1.2

1.0

0.8

0.6

0.4

0.2

1.9

INPUT DIFFERENTIAL (V p-p)

COMMON-MODE VOLTAGE (mV)

2.0

1.8

1.6

1.4

2.6

2.4

2.2

300

500

700

900

1100

1300

1500

FREQUENCY (MHz)

400

200

600

800

1000

1200

1400

1600

DIVIDER 1

DIVIDER 2 (FREQUENCY RANGE NORMALIZED FROM 0Hz TO 800MHz)

DIVIDER 3 (FREQUENCY RANGE NORMALIZED FROM 0Hz TO 500MHz)

100

110

120

130

140

150

SLEW RATE (V/ns)

–170

–160

–150

–140

–130

–120

–110

–100

–90

–80

100

10k

100k

10M

100M

FREQUENCY OFFSET (Hz)

HSTL 155.52MHz

HSTL 311.04MHz

HSTL 622.08MHz

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