AD9508PCBZ datasheet(22/40 Pages) AD

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AD9508

Data Sheet

Rev. A | Page 22 of 40

inputs have a resistor divider, which sets the common-mode

level. The complementary input is biased about 30 mV lower

than the true input to avoid oscillations in the event that the

input signal ceases. See Figure 42 for the equivalent differential

input circuit.

Figure 42. AD9508 Differential Input Stage

The inputs can be ac-coupled or dc-coupled in differential

mode. See Table 14 for input logic compatibility. The user can

supply a single-ended input with the input in differential mode

by ac or dc coupling to one side of the differential input and

bypassing the other input to ground by a capacitor.

Note that jitter performance degrades with low input slew rate,

as shown in Figure 25. See Figure 34 through Figure 37 for

different input clock termination schemes.

CLOCK OUTPUTS

Each channel output driver can be configured for either a

differential LVDS/HSTL output or two single-ended CMOS

outputs. When the LVDS/HSTL driver is enabled, the

corresponding CMOS driver is in tristate. When the CMOS

driver is enabled, the corresponding LVDS/HSTL driver is

powered down and tristated. See Figure 43 and Figure 44 for

the equivalent output stages.

Figure 43. LVDS/HSTL Output Simplified Equivalent Circuit

Figure 44. CMOS Equivalent Output Circuit

In LVDS or HSTL modes, there are register settings to control the

output logic type and current drive strength. The LVDS output

current can be set to the nominal 3.5 mA, additional settings

include 0.5, 0.75, 1.0 (default), and 1.25 multiplied by 3.5 mA.

The HSTL output current can be set to 8 mA (nominal) or

16 mA (double amplitude). For pin programming mode, see the

Pin Strapping to Program on Power-Up section for details and

limitations of the device. Under pin programming mode, the

nominal current is the default setting and is nonadjustable.

When routing single-ended CMOS signals, avoid driving multiple

input receivers with one output. Series termination at the source

is generally required to provide transmission line matching and/or

to reduce current transients at the driver. The value of the series

resistor is dependent on the board design and timing require-

ments (typically 10 Ω to 100 Ω). CMOS outputs are also limited in

terms of the capacitive load or trace length that they can drive.

Typically, trace lengths less than 3 inches are recommended to

preserve signal rise/fall times and signal integrity.

Figure 45. Series Termination of CMOS Output

Table 14. CLK and

CLKE

Differential Input Logic Compatibility

Supply (V)

Logic

Common Mode (V)

Output Swing (V)

AC-Coupled

DC-Coupled

3.3

CML

2.9

0.8

Yes

Not allowed

2.5

CML

2.1

0.8

Yes

Not allowed

1.8

CML

1.4

0.8

Yes

3.3

CMOS

1.65

3.3

Not allowed

Yes

2.51

CMOS

1.25

2.5

Not allowed

Yes

1.81

CMOS

0.9

1.8

Not allowed

Yes

1.5

HSTL

0.75

Yes

N/A

LVDS

1.25

0.4

Yes

3.3

LVPECL

2.0

0.8

Yes

Not allowed

2.5

LVPECL

1.2

0.8

Yes

1.8

LVPECL

0.5

0.8

Yes

IN_SEL is set for single-ended CMOS mode.

N/A means not applicable.

12.5kΩ

13kΩ

16.5kΩ

16kΩ

VDD

CLK

GND

OUTx

VDD

OUTxA

OUTxB

VDD

AD9508

CMOS

10Ω

60.4Ω

(1.0 INCH)

MICROSTRIP

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