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WM8985GEFL/R датащи(PDF) 17 Page - Wolfson Microelectronics plc

номер детали WM8985GEFL/R
подробное описание детали  Multimedia CODEC with Class D Headphone and Line Out
PDF  121 Pages
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производитель  WOLFSON [Wolfson Microelectronics plc]
домашняя страница  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8985GEFL/R датащи(HTML) 17 Page - Wolfson Microelectronics plc

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Production Data
WM8985
w
PD, Rev 4.6, July 2009
17
SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
MCLK
t
MCLKL
t
MCLKH
t
MCLKY
Figure 2 System Clock Timing Requirements
Test Conditions
DCVDD=1.8V, DBVDD=AVDD1=AVDD2=3.3V, DGND=AGND1=AGND2=0V, TA = +25
oC, Slave Mode
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
System Clock Timing Information
MCLK cycle time
TMCLKY
MCLK=SYSCLK (=256fs)
81.38
ns
MCLK input to PLL Note 1
20
ns
MCLK duty cycle
TMCLKDS
60:40
40:60
Note:
1.
PLL pre-scaling and PLL N and K values should be set appropriately so that SYSCLK is no greater than 12.288MHz.
AUDIO INTERFACE TIMING – MASTER MODE
Figure 3 Digital Audio Data Timing – Master Mode (see Control Interface)



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