WM8985GEFLSLASHR datasheet(79/121 Pages) WOLFSON

79 / 121 page

Production Data

WM8985

PD, Rev 4.6, July 2009

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R4 (04h)

Audio

Interface

Control

MONO

Selects between stereo and mono

device operation:

0 = Stereo device operation

1 = Mono device operation. Data

appears in ‘left’ phase of LRC only.

ALRSWAP

Controls whether ADC data appears in

‘right’ or ‘left’ phases of LRC clock:

0 = ADC left data appear in ‘left’ phase

of LRC and right data in ‘right’ phase

1 = ADC left data appear in ‘right’ phase

of LRC and right data in ‘left’ phase

DLRSWAP

Controls whether DAC data appears in

‘right’ or ‘left’ phases of LRC clock:

0 = DAC left data appear in ‘left’ phase

of LRC and right data in ‘right’ phase

1 = DAC left data appear in ‘right’ phase

of LRC and right data in ‘left’ phase

4:3

FMT

Audio interface Data Format Select:

00 = Right Justified

01 = Left Justified

10 = I2S format

11 = DSP/PCM mode

6:5

Word length

00 = 16 bits

01 = 20 bits

10 = 24 bits

11 = 32 bits (see note)

LRP

LRC clock polarity

0 = normal

1 =inverted

DSP Mode – mode A/B select

0 = MSB is available on 2nd BCLK rising

edge after LRC rising edge (mode A)

1 = MSB is available on 1

st BCLK rising

edge after LRC rising edge (mode B)

BCP

BCLK polarity

0 = normal

1 = inverted

LOOPBACK

Digital loopback function

0 = No loopback

1 = Loopback enabled, ADC data output

is fed directly into DAC data input.

Table 43 Audio Interface Control

Note:

Right Justified Mode will only operate with a maximum of 24 bits. If 32-bit mode is selected the

device will operate in 24-bit mode.

AUDIO INTERFACE CONTROL

The register bits controlling audio format, word length and master / slave mode are summarised

below.

and LRC are outputs. The frequency of BCLK in master mode can be controlled with BCLKDIV. The

frequencies of BCLK and LRC are also controlled by MCLKDIV. The LRC sample rate is set to the

required values by MCLKDIV and the BCLK rate will be set accordingly to provide sufficient BCLKs

for that chosen sample rate. These clocks are divided down versions of master clock.

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