WM8985GEFLSLASHR datasheet(39/121 Pages) WOLFSON

39 / 121 page

Production Data

WM8985

PD, Rev 4.6, July 2009

The polarity of the output signal can also be changed under software control using the

ADCLPOL/ADCRPOL register bit.

The oversampling rate of the ADC can be adjusted using the

ADCOSR128 register bit. With ADCOSR=0 the oversample rate is 64x which gives lowest power

operation and when ADCOSR=1 the oversample rate is 128x which gives best performance.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R14 (0Eh)

ADC Control

ADCLPOL

ADC left channel polarity adjust:

0 = normal

1 = inverted

ADCRPOL

ADC right channel polarity adjust:

0 = normal

1 = inverted

ADCOSR128

ADC oversample rate select:

0 = 64x (lower power)

1 = 128x (best performance)

Table 14 ADC Control

SELECTABLE HIGH PASS FILTER

A selectable high pass filter is provided and enabled as default. To disable this filter set HPFEN=0.

The filter has two modes controlled by HPFAPP. In Audio Mode (HPFAPP=0) the filter is first order,

with a cut-off frequency of 3.7Hz. In Application Mode (HPFAPP=1) the filter is second order, with a

cut-off frequency selectable via the HPFCUT register. The cut-off frequencies when HPFAPP=1 are

shown in Table 16.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R14 (0Eh)

ADC Control

6:4

HPFCUT

000

Application mode cut-off frequency

See Table 16 for details.

PLL Output Clock Division Ratio

00 = divide by 1

01 = divide by 2

10 = divide by 3

11 = divide by 4

Note: HPCUT and OPCLKDIV cannot be

set independently

HPFAPP

Select audio mode or application mode

0 = Audio mode (1st order, fc = ~3.7Hz)

1 = Application mode (2nd order, fc =

HPFCUT)

HPFEN

High Pass Filter Enable

0 = disabled

1 = enabled

Table 15 ADC Enable Control

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