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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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WM8985GEFL/R датащи(PDF) 82 Page - Wolfson Microelectronics plc |
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WM8985GEFL/R датащи(HTML) 82 Page - Wolfson Microelectronics plc |
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82 / 121 page  WM8985 Production Data w PD, Rev 4.6, July 2009 82 Figure 38 PLL and Clock Select Circuit The PLL frequency ratio R = f2/f1 (see Figure 38) can be set using the register bits PLLK and PLLN: PLLN = int R PLLK = int (224 (R-PLLN)) EXAMPLE: MCLK=12MHz, required clock = 12.288MHz. R should be chosen to ensure 5 < PLLN < 13. There is a fixed divide by 4 in the PLL and a selectable divide by N after the PLL which should be set to divide by 2 to meet this requirement. Enabling the divide by 2 sets the required f2 = 4 x 2 x 12.288MHz = 98.304MHz. R = 98.304 / 12 = 8.192 PLLN = int R = 8 k = int ( 224 x (8.192 – 8)) = 3221225 = 3126E9h REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R36 (24h) PLL N value 4 PLLPRESCALE 0 0 = MCLK input not divided (default) 1 = Divide MCLK by 2 before input to PLL 3:0 PLLN 1000 Integer (N) part of PLL input/output frequency ratio. Use values greater than 5 and less than 13. R37 (25h) PLL K value 1 5:0 PLLK [23:18] 0Ch Fractional (K) part of PLL1 input/output frequency ratio (treat as one 24-digit binary number). R38 (26h) PLL K Value 2 8:0 PLLK [17:9] 093h R39 (27h) PLL K Value 3 8:0 PLLK [8:0] 0E9h Table 47 PLL Frequency Ratio Control The PLL performs best when f2 is around 90MHz. Its stability peaks at N=8. Some example settings are shown in 48. |
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