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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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WM8985GEFL/R датащи(PDF) 96 Page - Wolfson Microelectronics plc |
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WM8985GEFL/R датащи(HTML) 96 Page - Wolfson Microelectronics plc |
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96 / 121 page  WM8985 Production Data w PD, Rev 4.6, July 2009 96 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 2 DLRSWAP 0 Controls whether DAC data appears in ‘right’ or ‘left’ phases of LRC clock: 0=DAC data appear in ‘left’ phase of LRC 1=DAC data appears in ‘right’ phase of LRC Digital Audio Interfaces 1 ALRSWAP 0 Controls whether ADC data appears in ‘right’ or ‘left’ phases of LRC clock: 0=ADC data appear in ‘left’ phase of LRC 1=ADC data appears in ‘right’ phase of LRC Digital Audio Interfaces 0 MONO 0 Selects between stereo and mono device operation: 0=Stereo device operation 1=Mono device operation. Data appears in ‘left’ phase of LRC Digital Audio Interfaces 5 (05h) 8:6 000 Reserved. Initialise to 0 5 WL8 0 Companding Control 8-bit mode 0=off 1=device operates in 8-bit mode Digital Audio Interfaces 4:3 DAC_COMP 00 DAC companding 00=off (linear mode) 01=reserved 10=μ-law 11=A-law Digital Audio Interfaces 2:1 ADC_COMP 00 ADC companding 00=off (linear mode) 01=reserved 10=μ-law 11=A-law Digital Audio Interfaces 0 LOOPBACK 0 Digital loopback function 0=No loopback 1=Loopback enabled, ADC data output is fed directly into DAC data input. Digital Audio Interfaces 6 (06h) 8 CLKSEL 1 Controls the source of the clock for all internal operation: 0=MCLK 1=PLL output Digital Audio Interfaces 7:5 MCLKDIV 010 Sets the scaling for either the MCLK or PLL clock output (under control of CLKSEL) 000=divide by 1 001=divide by 1.5 010=divide by 2 011=divide by 3 100=divide by 4 101=divide by 6 110=divide by 8 111=divide by 12 Digital Audio Interfaces |
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