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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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WM8985GEFL/R датащи(PDF) 71 Page - Wolfson Microelectronics plc |
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WM8985GEFL/R датащи(HTML) 71 Page - Wolfson Microelectronics plc |
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71 / 121 page  Production Data WM8985 w PD, Rev 4.6, July 2009 71 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R54 (36h) LOUT2 Volume control 5:0 LOUT2VOL 111001 Left output volume: (1dB steps) 000000 = -57dB ... 111001 = 0dB ... 111111 = +6dB 6 LOUT2MUTE 0 Left output mute: 0 = Normal operation 1 = Mute 7 LOUT2ZC 0 LOUT2 volume zero cross enable: 1 = Change gain on zero cross only 0 = Change gain immediately 8 OUT2VU Not latched LOUT2 and ROUT2 volumes do not update until a 1 is written to SPKVU (in reg 54 or 55) R55 (37h) ROUT2 Volume control 5:0 ROUT2VOL 111001 Right output volume: (1dB steps) 000000 = -57dB ... 111001 = 0dB ... 111111 = +6dB 6 ROUT2MUTE 0 Right output mute: 0 = Normal operation 1 = Mute 7 ROUT2ZC 0 ROUT2 volume zero cross enable: 1 = Change gain on zero cross only 0 = Change gain immediately 8 OUT2VU Not latched LOUT2 and ROUT2 volumes do not update until a 1 is written to SPKVU (in reg 54 or 55) Table 36 OUT2 Volume Control ZERO CROSS TIMEOUT A zero-cross timeout function is provided so that if zero cross is enabled on the input or output PGAs the gain will automatically update after a timeout period if a zero cross has not occurred. This is enabled by setting SLOWCLKEN. The timeout period is dependent on the clock input to the digital and is equal to 221 * SYSCLK period. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R7 (07h) Additional Control 0 SLOWCLKEN 0 Slow clock enable 0 = slow clock disabled 1 = slow clock enabled Table 37 Timeout Clock Enable Control Note: SLOWCLKEN is also used for the jack insert detect debounce circuit |
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