WM8985GEFLSLASHR datasheet(105/121 Pages) WOLFSON

105 / 121 page

Production Data

WM8985

PD, Rev 4.6, July 2009

105

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

PLLPRESCALE

0 = MCLK input not divided (default)

1 = Divide MCLK by 2 before input to PLL

Master Clock

and Phase

Locked Loop

(PLL)

3:0

PLLN[3:0]

1000

Integer (N) part of PLL input/output frequency

ratio. Use values greater than 5 and less than

13.

Master Clock

and Phase

Locked Loop

(PLL)

37 (25h)

8:6

000

Reserved. Initialise to 0

5:0

PLLK[23:18]

01100

Fractional (K) part of PLL1 input/output

frequency ratio (treat as one 24-digit binary

number).

Master Clock

and Phase

Locked Loop

(PLL)

38 (26h)

8:0

PLLK[17:9]

010010011

Fractional (K) part of PLL1 input/output

frequency ratio (treat as one 24-digit binary

number).

Master Clock

and Phase

Locked Loop

(PLL)

39 (27h)

8:0

PLLK[8:0]

011101001

Fractional (K) part of PLL1 input/output

frequency ratio (treat as one 24-digit binary

number).

Master Clock

and Phase

Locked Loop

(PLL)

41 (29h)

8:4

00000

Reserved. Initialise to 0

3:0

DEPTH3D

0000

Stereo depth

0000: 0% (minimum 3D effect)

0001: 6.67%

....

1110: 93.3%

1111: 100% (maximum 3D effect)

3D Stereo

Enhancement

42 (2Ah)

8:6

OUT4_2ADCVOL

000

Controls the OUT4 to ADC input boost stage:

000 = Path disabled (disconnected)

001 = -12dB gain

010 = -9dB gain

011 = -6dB gain

100 = -3dB gain

101 = +0dB gain

110 = +3dB gain

111 = +6dB gain

Analogue

Outputs

OUT4_2LNR

OUT4 to L or R ADC input

0 = Right ADC input

1 = Left ADC input

4:3

Reserved. Initialise to 0

POBCTRL

VMID independent current bias control

0 = Disable VMID independent current bias

1 = Enable VMID independent current bias

1:0

Reserved. Initialise to 0

43 (2Bh)

BYPL2RMIX

Left bypass path (from the Left channel input

PGA stage) to right output mixer

0 = not selected

1 = selected

Analogue

Outputs

BYPR2LMIX

Right bypass path (from the right channel input

PGA stage) to Left output mixer

0 = not selected

1 = selected

Analogue

Outputs

Reserved. Initialise to 0

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