LPC810M021FN8 datasheet(13/313 Pages) NXP

13 / 313 page

UM10601

All information provided in this document is subject to legal disclaimers.

Preliminary user manual

Rev. 1.0 — 7 November 2012

13 of 313

4.1 How to read this chapter

The system configuration block is identical for all LPC800 parts. USART2 and SPI1 are

only available on parts LPC812M101FDH20 and LPC812M101FDH16 and the corresponding

clocks, reset, and wake-up control bits are reserved for all other parts.

4.2 Features

• Clock control

• Reset control

• Pin interrupt set-up

• Configuration of reduced power modes

• Wake-up control

• BOD configuration

4.3 Basic configuration

Configure the SYSCON block as follows:

• The SYSCON uses the CKIN, CLKOUT, RESET, and XTALIN/OUT pins. Configure

the pin functions through the switch matrix. See Section 4.4.

• No clock configuration is needed. The clock to the SYSCON block is always enabled.

By default, the SYSCON block is clocked by the IRC.

4.3.1 Set up the PLL

The PLL creates a stable output clock at a higher frequency than the input clock. If you

need a main clock with a frequency higher than the 12 MHz IRC clock, use the PLL to

boost the input frequency.

1. Power up the system PLL in the PDRUNCFG register.

Section 4.6.32 “Power configuration register”

2. Select the PLL input in the SYSPLLCLKSEL register. You have the following input

options:

–

IRC: 12 MHz internal oscillator.

–

System oscillator: External crystal oscillator using the XTALIN/XTALOUT pins.

–

External clock input CLKIN. Select this pin through the switch matrix.

Section 4.6.8 “System PLL clock source select register”

3. Update the PLL clock source<tbd> in the SYSPLLCKUEN register.

Section 4.6.9 “System PLL clock source update register”

4. Configure the PLL M and N dividers.

Section 4.6.3 “System PLL control register”

UM10601

Chapter 4: LPC800 System configuration (SYSCON)

Rev. 1.0 — 7 November 2012

Preliminary user manual

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