LPC810M021FN8 datasheet(63/313 Pages) NXP

63 / 313 page

UM10601

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Preliminary user manual

Rev. 1.0 — 7 November 2012

63 of 313

NXP Semiconductors

UM10601

Chapter 6: LPC800 I/O configuration (IOCON)

6.5.6 PIO0_3 register

Table 54.

PIO0_3 register (PIO0_3, address 0x4004 4014) bit description

Bit

Symbol

Value

Description

Reset

value

2:0

Reserved.

4:3

MODE

Selects function mode (on-chip pull-up/pull-down resistor

control).

0b10

0x0

Inactive (no pull-down/pull-up resistor enabled).

0x1

Pull-down resistor enabled.

0x2

Pull-up resistor enabled.

0x3

Repeater mode.

HYS

Hysteresis.

Disable.

Enable.

INV

Invert input.

Input not inverted (HIGH on pin reads as 1; LOW on pin

reads as 0).

Input inverted (HIGH on pin reads as 0, LOW on pin reads as

1).

9:7

Reserved.

0b001

Open-drain mode.

Disable.

Open-drain mode enabled.

Remark:

This is not a true open-drain mode.

12:11

S_MODE

Digital filter sample mode.

0x0

Bypass input filter.

0x1

1 clock cycle. Input pulses shorter than one filter clock are

rejected.

0x2

2 clock cycles. Input pulses shorter than two filter clocks are

rejected.

0x3

3 clock cycles. Input pulses shorter than three filter clocks

are rejected.

15:13 CLK_DIV

Select peripheral clock divider for input filter sampling clock.

Value 0x7 is reserved.

0x0

IOCONCLKDIV0.

0x1

IOCONCLKDIV1.

0x2

IOCONCLKDIV2.

0x3

IOCONCLKDIV3.

0x4

IOCONCLKDIV4.

0x5

IOCONCLKDIV5.

0x6

IOCONCLKDIV6.

31:16 -

Reserved.

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