LPC810M021FN8 datasheet(33/313 Pages) NXP

33 / 313 page

UM10601

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Preliminary user manual

Rev. 1.0 — 7 November 2012

33 of 313

NXP Semiconductors

UM10601

Chapter 4: LPC800 System configuration (SYSCON)

4.6.28 Start logic 0 pin wake-up enable register

The STARTERP0 register enables the selected pin interrupts for wake-up from

deep-sleep mode and power-down modes.

Remark:

Also enable the corresponding interrupts in the NVIC. See Table 3 “Connection

of interrupt sources to the NVIC”.

Table 32.

Pin interrupt select registers (PINTSEL[0:7], address 0x4004 8178 (PINTSEL0) to

0x4004 8194 (PINTSEL7)) bit description

Bit

Symbol

Description

Reset

value

5:0

INTPIN

Pin number select for pin interrupt or pattern match engine input.

(PIO0_0 to PIO0_17 correspond to numbers 0 to 17).

31:6

Reserved

Table 33.

Start logic 0 pin wake-up enable register 0 (STARTERP0, address 0x4004 8204) bit

description

Bit

Symbol

Value

Description

Reset

value

PINT0

GPIO pin interrupt 0 wake-up

Disabled

Enabled

PINT1

GPIO pin interrupt 1 wake-up

Disabled

Enabled

PINT2

GPIO pin interrupt 2 wake-up

Disabled

Enabled

PINT3

GPIO pin interrupt 3 wake-up

Disabled

Enabled

PINT4

GPIO pin interrupt 4 wake-up

Disabled

Enabled

PINT5

GPIO pin interrupt 5 wake-up

Disabled

Enabled

PINT6

GPIO pin interrupt 6 wake-up

Disabled

Enabled

PINT7

GPIO pin interrupt 7 wake-up

Disabled

Enabled

31:8

Reserved

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