LPC810M021FN8 datasheet(39/313 Pages) NXP

39 / 313 page

UM10601

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Preliminary user manual

Rev. 1.0 — 7 November 2012

39 of 313

NXP Semiconductors

UM10601

Chapter 4: LPC800 System configuration (SYSCON)

4.7.1.1 Lock detector

The lock detector measures the phase difference between the rising edges of the input

and feedback clocks. Only when this difference is smaller than the so called “lock

criterion” for more than eight consecutive input clock periods, the lock output switches

from low to high. A single too large phase difference immediately resets the counter and

causes the lock signal to drop (if it was high). Requiring eight phase measurements in a

row to be below a certain figure ensures that the lock detector will not indicate lock until

both the phase and frequency of the input and feedback clocks are very well aligned. This

effectively prevents false lock indications, and thus ensures a glitch free lock signal.

4.7.1.2 Power-down control

To reduce the power consumption when the PLL clock is not needed, a Power-down

mode has been incorporated. This mode is enabled by setting the SYSPLL_PD bit to one

in the Power-down configuration register (Table 37). In this mode, the internal current

reference will be turned off, the oscillator and the phase-frequency detector will be

stopped and the dividers will enter a reset state. While in Power-down mode, the lock

output will be low to indicate that the PLL is not in lock. When the Power-down mode is

terminated by setting the SYSPLL_PD bit to zero, the PLL will resume its normal

operation and will make the lock signal high once it has regained lock on the input clock.

4.7.1.3 Divider ratio programming

4.7.1.3.1

Post divider

The division ratio of the post divider is controlled by the PSEL bits. The division ratio is two

times the value of P selected by PSEL bits as shown in Table 8. This guarantees an

output clock with a 50% duty cycle.

4.7.1.3.2

Feedback divider

The feedback divider’s division ratio is controlled by the MSEL bits. The division ratio

between the PLL’s output clock and the input clock is the decimal value on MSEL bits plus

one, as specified in Table 8 .

4.7.1.3.3

Changing the divider values

Changing the divider ratio while the PLL is running is not recommended. As there is no

way to synchronize the change of the MSEL and PSEL values with the dividers, the risk

exists that the counter will read in an undefined value, which could lead to unwanted

spikes or drops in the frequency of the output clock. The recommended way of changing

between divider settings is to power down the PLL, adjust the divider settings and then let

the PLL start up again.

4.7.1.4 Frequency selection

The PLL frequency equations use the following parameters (also see Figure 4):

Table 39.

PLL frequency parameters

Parameter

System PLL

FCLKIN

Frequency of sys_pllclkin (input clock to the system PLL) from the

SYSPLLCLKSEL multiplexer (see Section 4.6.8).

FCCO

Frequency of the Current Controlled Oscillator (CCO); 156 to 320 MHz.

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