LPC810M021FN8 datasheet(97/313 Pages) NXP

97 / 313 page

UM10601

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Preliminary user manual

Rev. 1.0 — 7 November 2012

97 of 313

NXP Semiconductors

UM10601

Chapter 8: LPC800 Pin interrupts/pattern match engine

25:23 CFG5

Specifies the match-contribution condition for bit slice 5.

0b000

0x0

Constant 1. This bit slice always contributes to a product term match.

0x1

Rising edge. Match occurs if a rising edge on the specified input has occurred since

the last time the edge detection for this bit slice was cleared.

This bit is only

cleared when the PMCFG or the PMSRC registers are written to.

0x2

Falling edge. Match occurs if a falling edge on the specified input has occurred since

the last time the edge detection for this bit slice was cleared.

This bit is only

cleared when the PMCFG or the PMSRC registers are written to.

0x3

Rising or falling edge. Match occurs if either a rising or falling edge on the specified

input has occurred since the last time the edge detection for this bit slice was

cleared.

This bit is only cleared when the PMCFG or the PMSRC registers

are written to.

0x4

High level. Match (for this bit slice) occurs when there is a high level on the input

specified for this bit slice in the PMSRC register.

0x5

Low level. Match occurs when there is a low level on the specified input.

0x6

Constant 0. This bit slice never contributes to a match (should be used to disable

any unused bit slices)

0x7

Event. Match occurs on an event - i.e. when either a rising or falling edge is first

detected on the specified input (this is a non-sticky version of option 3)

28:26 CFG6

Specifies the match-contribution condition for bit slice 6.

0b000

0x0

Constant 1. This bit slice always contributes to a product term match.

0x1

Rising edge. Match occurs if a rising edge on the specified input has occurred since

the last time the edge detection for this bit slice was cleared.

This bit is only

cleared when the PMCFG or the PMSRC registers are written to.

0x2

Falling edge. Match occurs if a falling edge on the specified input has occurred since

the last time the edge detection for this bit slice was cleared.

This bit is only

cleared when the PMCFG or the PMSRC registers are written to.

0x3

Rising or falling edge. Match occurs if either a rising or falling edge on the specified

input has occurred since the last time the edge detection for this bit slice was

cleared.

This bit is only cleared when the PMCFG or the PMSRC registers

are written to.

0x4

High level. Match (for this bit slice) occurs when there is a high level on the input

specified for this bit slice in the PMSRC register.

0x5

Low level. Match occurs when there is a low level on the specified input.

0x6

Constant 0. This bit slice never contributes to a match (should be used to disable

any unused bit slices)

0x7

Event. Match occurs on an event - i.e. when either a rising or falling edge is first

detected on the specified input (this is a non-sticky version of option 3)

Table 92.

Pattern match bit slice configuration register (PMCFG, address 0x4004 C030) bit description …continued

Bit

Symbol

Value

Description

Reset

value

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