LPC810M021FN8 datasheet(21/313 Pages) NXP

21 / 313 page

UM10601

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Preliminary user manual

Rev. 1.0 — 7 November 2012

21 of 313

NXP Semiconductors

UM10601

Chapter 4: LPC800 System configuration (SYSCON)

4.6.4 System PLL status register

This register is a Read-only register and supplies the PLL lock status (see <tbd>).

4.6.5 System oscillator control register

This register configures the frequency range for the system oscillator.

Table 8.

System PLL control register (SYSPLLCTRL, address 0x4004 8008) bit description

Bit

Symbol

Value

Description

Reset

value

4:0

MSEL

Feedback divider value. The division value M is the

programmed MSEL value + 1.

00000: Division ratio M = 1

11111: Division ratio M = 32

6:5

PSEL

Post divider ratio P. The division ratio is 2

 P.

0x0

P = 1

0x1

P = 2

0x2

P = 4

0x3

P = 8

31:7

Reserved. Do not write ones to reserved bits.

Table 9.

System PLL status register (SYSPLLSTAT, address 0x4004 800C) bit description

Bit

Symbol

Value

Description

Reset

value

LOCK

PLL lock status

PLL not locked

PLL locked

31:1

Reserved

Table 10.

System oscillator control register (SYSOSCCTRL, address 0x4004 8020) bit

description

Bit

Symbol

Value

Description

Reset

value

BYPASS

Bypass system oscillator

0x0

Disabled. Oscillator is not bypassed.

Enabled. PLL input (sys_osc_clk) is fed directly

from the XTALIN pin bypassing the oscillator. Use

this mode when using an external clock source

instead of the crystal oscillator.

FREQRANGE

Determines frequency range for Low-power

oscillator.

0x0

1 - 20 MHz frequency range.

15 - 25 MHz frequency range

31:2

Reserved

0x00

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