LPC810M021FN8 datasheet(32/313 Pages) NXP

32 / 313 page

UM10601

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Preliminary user manual

Rev. 1.0 — 7 November 2012

32 of 313

NXP Semiconductors

UM10601

Chapter 4: LPC800 System configuration (SYSCON)

4.6.26 NMI source selection register

The NMI source selection register selects a peripheral interrupts as source for the NMI

interrupt of the ARM Cortex-M0+ core. For a list of all peripheral interrupts and their IRQ

numbers see <tbd>. For a description of the NMI functionality, see <tbd>.

Note:

If the NMISRC register is used to select an interrupt as the source of Non-Maskable

interrupts, and the selected interrupt is enabled, one interrupt request can result in both a

Non-Maskable and a normal interrupt. This can be avoided by disabling the normal

interrupt in the NVIC, as described in <tbd>.

4.6.27 Pin interrupt select registers

Each of these 8 registers selects one pin from all digital pins as the source of a pin

interrupt or as the input to the pattern match engine. To select a pin for any of the eight pin

interrupts or pattern match engine inputs, write the GPIO port pin number as 0 to 17 for

pins PIO0_0 to PIO0_17 to the INTPIN bits. For example, setting INTPIN to 0x5 in

PINTSEL0 selects pin PIO0_5 for pin interrupt 0.

To determine the GPIO port pin number on a given LPC800 package, see the pin

description table in the data sheet.

Remark:

The GPIO port pin number serves to identify the pin to the PINTSEL register.

Any digital function, including GPIO, can be assigned to this pin through the switch matrix.

Each of the 8 pin interrupts must be enabled in the NVIC using interrupt slots # 24 to 31

(see Table 3).

To use the selected pins for pin interrupts or the pattern match engine, see Section 8.5.2

“Pattern match engine”.

Table 30.

IRQ latency register (IRQLATENCY, address 0x4004 8170) bit description

Bit

Symbol

Description

Reset

value

7:0

LATENCY

8-bit latency value

0x010

31:8

Reserved

Table 31.

NMI source selection register (NMISRC, address 0x4004 8174) bit description

Bit

Symbol Description

Reset

value

4:0

IRQNO The IRQ number of the interrupt that acts as the Non-Maskable Interrupt

(NMI) if bit 31 is 1. See Table 3 for the list of interrupt sources and their

IRQ numbers.

30:5

Reserved

NMIEN

Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source

selected by bits 4:0.

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