LPC810M021FN8 datasheet(49/313 Pages) NXP

49 / 313 page

UM10601

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Preliminary user manual

Rev. 1.0 — 7 November 2012

49 of 313

NXP Semiconductors

UM10601

Chapter 5: LPC800 Reduced power modes and Power Management

5.7.5.2 Programming Deep-sleep mode

The following steps must be performed to enter Deep-sleep mode:

1. The PD bits in the PCON register must be set to 0x1 (Table 43).

2. Select the power configuration in Deep-sleep mode in the PDSLEEPCFG (Table 35)

3. Select the power configuration after wake-up in the PDAWAKECFG (Table 36)

4. If any of the available wake-up interrupts are needed for wake-up, enable the

interrupts in the interrupt wake-up registers (Table 33, Table 34) and in the NVIC.

5. Write one to the SLEEPDEEP bit in the ARM Cortex-M0 SCR register.

6. Use the ARM WFI instruction.

5.7.5.3 Wake-up from Deep-sleep mode

The microcontroller can wake up from Deep-sleep mode in the following ways:

• Signal on one of the eight pin interrupts selected in Table 32. Each pin interrupt must

also be enabled in the STARTERP0 register (Table 33) and in the NVIC.

• BOD signal, if the BOD is enabled in the PDSLEEPCFG register:

–

BOD interrupt using the deep-sleep interrupt wake-up register 1 (Table 34). The

BOD interrupt must be enabled in the NVIC. The BOD interrupt must be selected in

the BODCTRL register.

–

Reset from the BOD circuit. In this case, the BOD circuit must be enabled in the

PDSLEEPCFG register, and the BOD reset must be enabled in the BODCTRL

• WWDT signal, if the watchdog oscillator is enabled in the PDSLEEPCFG register:

–

WWDT interrupt using the interrupt wake-up register 1 (Table 34). The WWDT

interrupt must be enabled in the NVIC. The WWDT interrupt must be set in the

WWDT MOD register.

–

Reset from the watchdog timer. The WWDT reset must be set in the WWDT MOD

(see PDSLEEPCFG register), and the WDT must be enabled in the

SYSAHBCLKCTRL register.

• Via any of the USART blocks. See Section 15.3.2 “Configure the USART for

wake-up”.

• Via the I2C. See <tbd>.

• Via any of the SPI blocks. See <tbd>.

Remark:

If the watchdog oscillator is running in Deep-sleep mode, its frequency

determines the wake-up time.

5.7.6 Power-down mode

In Power-down mode, the system clock to the processor is disabled as in Sleep mode. All

analog blocks are powered down, except for the BOD circuit and the watchdog oscillator,

which must be selected or deselected during Power-down mode in the PDSLEEPCFG

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