DAC5687MPZPEP datasheet(64/75 Pages) TI1

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Schematic and Layout Recommendations

Application Examples

Application Example: Real IF Radio

DAC5687-EP

SGLS333 – JUNE 2006

First, the location of the spurious signals is found for the X2 real output in Figure 68(b). One spurious signals is

present in the range 0 to 0.5

× f

DAC at 0.325 × fDAC (see Table 16). Consulting Figure 72(a), the raw amplitude

for fDAC/2 is 47 dBc. From Figure 73, the amplitude adjustment factor for fSIG = 0.175 × fDAC is estimated at ~ 6

dB, and so the fDAC/2 and fDAC/4 is adjusted to 53 dBc.

Table 16. Example # 2 for Calculating Spurious Signals

Spurious

Frequency/fDAC

Frequency

Raw Amplitude (dBc)

Adjusted Amplitude (dBc)

Signal

(MHz)

fDAC/2

0.325

130

The DAC5687 clock is sensitive to fast transitions of input data on pins DA0, DA1, and DA2 (55, 54, and 53) due

to coupling to DVDD pin 56. The noise-like spectral energy of the DA[0–2] couples into the DAC clock, resulting

in increased jitter. This significantly improves by using a 10-

Ω resistor between DVDD and pin 56 in addition to

10-pF capacitor to DGND, as implemented on the DAC5687EVM (see the DAC5687 EVM user's guide, TI

literature number SLWU017). Pin 56 draws only approximately 2 mA of current and the 0.02-V voltage drop

across the resistor is acceptable for DVDD voltages within the MINIMUM and MAXIMUM specifications. It is also

recommended that the transition rate of the input lines be slowed by inserting series resistors near the data

source. The optimized value of the series resistor depends on the capacitance of the trace between the series

resistor and DAC5687 input pin. For a 2 inch to 3 inch trace, a 22-

Ω to 47-Ω resistor would be recommended.

The effect of DAC clock jitter on the DAC output signal is worse for signals at higher signal frequencies. For low

IF (< 75 MHz) or baseband signals, there is little degradation of the output signal. However, for high IF (> 75

MHz) the DAC clock jitter may result in an elevated noise floor, which often appears as broad humps in the DAC

output spectrum. It is recommended for signals above 75 MHz that the inputs to DA0 and DA1, which are the

two LSBs if input DA[0–15] is not reversed, not be connected to input data to prevent coupling to the DAC rate

clock. The decrease in resolution to 14-bits and increase in quantization noise will not significantly affect the

DAC5687 SNR for signals > 75 MHz.

An system example of the DAC5687 used for a flexible real IF radio is shown in Figure 74. A complex baseband

input to the DAC would be generated by a digital upconverter such as Texas Instruments GC4116, GC5016, or

GC5316. The DAC5687 would be used to increase the data rate through interpolation and flexibly place the

output signal using the FMIX and/or CMIX blocks. Although the DAC5687 X4 mode is shown, any of the modes

(x2, x4L, or x8) would be appropriate.

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