DAC5687MPZPEP datasheet(41/75 Pages) TI1

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ΣΣ

qmb_offset

{−4096, −4095,

… , 4095 }

qma_offset

{−4096, −4095,

… , 4095 }

Analog DAC Gain

fullscale +

16 V

extio

BIAS

GAINCODE ) 1

B 1 *

FINEGAIN

3072

Clock Modes

DAC5687-EP

SGLS333 – JUNE 2006

Figure 43. DAC Offset Block

The full-scale DAC output current can be set by programming the daca_gain and dacb_gain registers. The

DAC gain value controls the full-scale output current.

where GAINCODE = daca_gain[11:8] or dacb_gain[11:8] is the coarse gain setting ( 0 to 15) and FINEGAIN =

daca_gain[7:0] or dacb_gain[7:0] (–128 to 127) is the fine gain setting.

In the DAC5687, the internal clocks (1x, 2x, 4x, and 8x as needed) for the logic, FIR interpolation filters, and

DAC are derived from a clock at either the input data rate using an internal PLL (PLL clock mode) or DAC output

sample rate (external clock mode). Power for the internal PLL blocks (PLLVDD and PLLGND) are separate from

the other clock generation blocks power (CLKVDD and CLKGND), thus minimizing phase noise within the PLL.

The DAC5687 has three clock modes for generating the internal clocks (1x, 2x, 4x, and 8x as needed) for the

logic, FIR interpolation filters, and DACs. The clock mode is set using the PLLVDD pin and dual_clk in register

CONFIG1.

1. PLLVDD = 0 V and dual_clk = 0: EXTERNAL CLOCK MODE

In EXTERNAL CLOCK MODE, the user provides a clock signal at the DAC output sample rate through

CLK2/CLK2C. CLK1/CLK1C and the internal PLL are not used. LPF and CLK1/CLK1C pins can be left

unconnected. The input data rate clock and interpolation rate are selected by the bits interp(1:0) in register

CONFIG0 and is output through the PLLLOCK pin. The PLLLOCK clock can be used to drive the input data

source (such as digital upconverter) that sends the data to the DAC. Note that the PLLLOCK delay relative to

the input CLK2 rising edge (td(PLLLOCK)) in Figure 44 and Figure 45) increases with increasing loads. The input

data is latched on either the rising (inv_plllock = 0) or falling edge (inv_plllock = 1) of PLLLOCK, which is

sensed internally at the output pin.

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