DAC5687MPZPEP datasheet(28/75 Pages) TI1

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DAC5687-EP

SGLS333 – JUNE 2006

Table 3. Coarse Mixer Sequences (continued)

cm_mode(3:0)

Mixing Mode

Sequence

1000

fDAC/4

DAC A = {+A –B –A +B

…}

DAC B = {+B +A –B –A

…}

1001

fDAC/4

DAC A = {+A –B –A +B

…}

DAC B = {–B –A +B +A

…}

1010

fDAC/4

DAC A = {–A +B +A –B

…}

DAC B = {+B +A –B –A

…}

1011

fDAC/4

DAC A = {–A +B +A –B

…}

DAC B = {–B –A +B +A

…}

1100

–fDAC/4

DAC A = {+A +B –A –B

…}

DAC B = {+B –A –B +A

…}

1101

–fDAC/4

DAC A = {+A +B –A –B

…}

DAC B = {–B +A +B –A

…}

1110

–fDAC/4

DAC A = {–A –B +A +B

…}

DAC B = {+B –A –B +A

…}

1111

–fDAC/4

DAC A = {–A –B +A +B

…}

DAC B = {–B +A +B –A

…}

invsinc:

Enables the invsinc compensation filter when set.

BIT 7

BIT 0

sif_4pin

dac_ser_data

half_rate

Unused

usb

counter_mode(2:0)

sif_4pin:

Four-pin serial interface mode is enabled when set, 3-pin mode when cleared.

dac_ser_data: When set, both DAC A and DAC B input data is replaced with fixed data loaded into the 16 bit

serial interface ser_data register.

half_rate:

Enables half-rate input mode. Input data for the DAC A data path is input to the chip at half speed

using both the DA(15:0) and DB(15:0) input pins.

usb:

When set, the data to DACB is inverted to generate upper side band output.

counter_mode(2:0): Controls

the

internal

counter

that

can

used

the

DAC

data

source.

{0XX = off; 100 = all 16b; 101 = 7b LSBs; 110 = 5b MIDs; 111 = 5b MSBs}

BIT 7

BIT 0

sync_phstr

sync_nco

sync_cm

sync_fifo(2:0)

unused

sync_phstr: When set, the internal clock divider logic is initialized with a PHSTR pin low-to-high transition.

sync_nco:

When set, the NCO phase accumulator is cleared with a PHSTR low-to-high transition.

sync_cm:

When set, the coarse mixer is initialized with a PHSTR low-to-high transition.

sync_fifo(2:0): Sync source selection mode for the FIFO. When a low-to-high transition is detected on the

selected sync source, the FIFO input and output pointers are initialized.

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