DAC5687MPZPEP datasheet(51/75 Pages) TI1

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DAC Transfer Function

Analog Current Outputs

DAC5687-EP

SGLS333 – JUNE 2006

The full-scale output current can be adjusted from 20 mA down to 2 mA by varying resistor RBIAS or changing

the externally applied reference voltage. The internal control amplifier has a wide input range, supporting the

full-scale output current range of 20 mA.

The CMOS DAC’s consist of a segmented array of NMOS current sinks, capable of sinking a full-scale output

current up to 20 mA. Differential current switches direct the current of each current source through either one of

the complementary output nodes IOUT1 or IOUT2. Complementary output currents enable differential operation,

thus canceling out common mode noise sources (digital feed-through, on-chip and PCB noise), dc offsets, even

order distortion components, and increasing signal output power by a factor of two.

The full-scale output current is set using external resistor RBIAS in combination with an on-chip bandgap-voltage

reference source (1.2 V) and control amplifier. Current IBIAS through resistor RBIAS is mirrored internally to

provide a full-scale output current equal to 16 times IBIAS. The full-scale current IOUTFS can be adjusted from

20 mA down to 2 mA.

The relation between IOUT1 and IOUT2 can be expressed as:

IOUT1 = –IOUTFS – IOUT2

We denote current flowing into a node as negative current and current flowing out of a node as positive current.

Since the output stage is a current sink the current can only flow from AVDD into the IOUT1 and IOUT2 pins. If

IOUT2 = –5 mA and IO(FS) = 20 mA then:

IOUT1 = –20 – (–5) = –15 mA

The output current flow in each pin driving a resistive load can be expressed as:

IOUT1 = IOUTFS × CODE / 65536

IOUT2 = IOUTFS × (65535 – CODE) / 65536

where CODE is the decimal representation of the DAC data input word.

For the case where IOUT1 and IOUT2 drive resistor loads RL directly, this translates into single ended voltages

at IOUT1 and IOUT2:

VOUT1 = AVDD – I IOUT1 I × RL

VOUT2 = AVDD – I IOUT2 I × RL

Assuming that the data is full scale (65535 in offset binary notation) and the RL is 25 Ω, the differential voltage

between pins IOUT1 and IOUT2 can be expressed as:

VOUT1 = AVDD – I –20 mA I

× 25 Ω = 2.8 V

VOUT2 = AVDD – I –0 mA I

× 25 Ω = 3.3 V

VDIFF = VOUT1 – VOUT2 = 0.5 V

Note that care should be taken not to exceed the compliance voltages at node IOUT1 and IOUT2, which would

lead to increased signal distortion.

Figure 57 shows a simplified schematic of the current source array output with corresponding switches.

Differential switches direct the current of each individual NMOS current source to either the positive output node

IOUT1 or its complementary negative output node IOUT2. The output impedance is determined by the stack of

the current sources and differential switches, and is typically >300 k

Ω in parallel with an output capacitance of 5

pF.

The external output resistors are referred to an external ground. The minimum output compliance at nodes

IOUT1 and IOUT2 is limited to AVDD – 0.5 V, determined by the CMOS process. Beyond this value, transistor

breakdown may occur resulting in reduced reliability of the DAC5687 device. The maximum output compliance

voltage at nodes IOUT1 and IOUT2 equals AVDD + 0.5 V. Exceeding the minimum output compliance voltage

adversely affects distortion performance and integral non-linearity. The optimum distortion performance for a

single-ended or differential output is achieved when the maximum full-scale signal at IOUT1 and IOUT2 does

not exceed 0.5 V.

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