DAC5687MPZPEP datasheet(48/75 Pages) TI1

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PHSTR

clk_in

clk_out

phstr at FIFO

output

clk_nco

phase

accumulator

reset

phase_accum

only needs to be asserted for one clk_in period

Input delay line + FIFO delay

13 clk_nco cycles

Coarse Mixer (CMIX) Synchronization

DAC5687-EP

SGLS333 – JUNE 2006

The serial interface includes a sync_nco bit in register SYNC_CNTL, which needs to be set for the PHSTR

input signal to initialize the phase accumulator.

The NCO uses a rising edge detector to perform the synchronous reset of the phase accumulator. Due to the

pipelined nature of the NCO, the latency from the phstr sync signal at the FIFO output to the instant the phase

accumulator is cleared is 13 fNCO clock cycles (fNCO = fDAC in X4 mode, fNCO = fDAC/2 in X2, X4L, and X8 modes).

In 2x interpolation mode with the inverse sinc filter disabled, overall latency from PHSTR input to DAC output is

~100 input clock cycles.

Figure 53. NCO Phase Accumulator Reset Synchronization Timing

The coarse mixer implements the fDAC/2 and fDAC/4 (and – fDAC/4) fixed complex mixing operation using simple

complements of the datapath signals to create the proper sequences. The sequences are controlled using a

simple counter and this counter can be synchronously reset using the PHSTR signal.

Similar to the NCO, the PHSTR signal used by the coarse mixer is from the FIFO output. This introduces the

same uncertainty effect due to the FIFO input to output pointer relationship. Bypassing the FIFO and using the

dual external clock mode without FIFO eliminates this uncertainty for systems using multiple DAC5687 devices

when this cannot be tolerated. Using the internal PLL, as with the NCO, allows the complete control and

synchronization of the coarse mixer.

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