DAC5687MPZPEP datasheet(42/75 Pages) TI1

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PLLLOCK

CLK2

DA[15:0]

DB[15:0]

td(PLLLOCK)

th(DATA)

ts(DATA)

AN+1

BN+1

PLLLOCK

CLK2

DA[15:0]

DB[15:0]

td(PLLLOCK)

th(DATA)

ts(DATA)

AN+1

BN+1

DAC5687-EP

SGLS333 – JUNE 2006

Figure 44. Dual Bus Mode Timing Diagram for External Clock Mode (PLLLOCK Rising Edge)

Figure 45. Dual Bus Mode Timing Diagram for External Clock Mode (PLLLOCK Falling Edge)

2. PLLVDD = 3.3 V (dual_clk can be 0 or 1 and is ignored): PLL CLOCK MODE

In PLL CLOCK MODE, you drive the DAC at the input sample rate (unless the data is mux’d) through

CLK1/CLK1C. CLK2/CLK2C is not used. In this case, there is no phase ambiguity on the clock. The DAC

generates the higher speed DAC sample rate clock using an internal PLL/VCO. In PLL clock mode, the user

provides a differential external reference clock on CLK1/CLK1C.

A type four phase-frequency detector (PFD) in the internal PLL compares this reference clock to a feedback

clock and drives the PLL to maintain synchronization between the two clocks. The feedback clock is generated

by dividing the VCO output by 1x, 2x, 4x, or 8x as selected by the prescaler (div[1:0]). The output of the

prescaler is the DAC sample rate clock and is divided down to generate clocks at ÷ 2, ÷4, and ÷ 8. The feedback

clock is selected by the registers sel(1:0), which is fed back to the PFD for synchronization to the input clock.

The feedback clock is also used for the data input rate, so the ratio of DAC output clock to feedback clock sets

the interpolation rate of the DAC5687. The PLLLOCK pin is an output indicating when the PLL has achieved

lock. An external RC low-pass PLL filter is provided by the user at pin LPF. See the Low-Pass Filter section for

filter setting calculations. This is the only mode where the LPF filter applies.

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