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DAC5687MPZPEP датащи(PDF) 45 Page - Texas Instruments

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номер детали DAC5687MPZPEP
подробное описание детали  16-BIT 500-MSPS 2쨈??쨈 INTERPOLATING DUAL-CHANNEL DIGITAL-TO-ANALOG CONVERTER (DAC)
PDF  75 Pages
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производитель  TI1 [Texas Instruments]
домашняя страница  http://www.ti.com
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DAC5687MPZPEP датащи(HTML) 45 Page - Texas Instruments

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0
1
S
DA(15:0),
DB(15:0),
PHSTR
0
1
D Q
input
pointer
generation
PLLLOCK
MUX
CLK1
CLK1C
{PLLVDD,
inv_plllock, dual_clk}
MUX
clock
generator
resynchonized
da(15:0), db(15:0)
and phstr
sync source
{TXENABLE, PHSTR, QFLAG, DB(15),
DA(15) oneshot, SIF write, always off}
CLK2
CLK2C
PLL VCO
1
fifo_bypass
in_sel_d
in_sel_c
in_sel_b
in_sel_a
q_b
q_c
q_d
q_in
q_out
clk_in
clk_out
sel_q_a
sel_q_d
sel_q_c
sel_q_b
sync
D Q
DA(15:0),
DB(15:0),
PHSTR
0
1
S
D Q
S
0
1
S
D Q
,
output
pointer
generation
Q
D
DA(15) oneshot
0
Q
D
S
q_a
DAC5687-EP
SGLS333 – JUNE 2006
Figure 50. DAC5687 Input FIFO Logic
Initialization of the FIFO block involves selecting and asserting a synchronization source. Initialization causes the
input and output pointers to be forced to an offset of 2; the input pointer will be forced to the in_sel_a state while
the output pointer will be forced to the sel_q_c state. This initialization of the input and output pointers can cause
discontinuities in a data stream and should therefore be handled at startup.
Table 11. Synchronization Source Selection
sync_fifo (2:0)
Synchronization Source
000
txenable pin
001
phstr pin
010
qflag pin
011
db(15)
100
da(15) first transition (one shot)
101
sync now with SIF write (always on)
110
sync source disabled (always off)
111
sync now with SIF write (always on)
45
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