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NCO Synchronization

PHSTR

PLLLOCK

MUX

CLK1

CLK1C

{PLLVDD, inv_plllock, dual_clk}

clk_in

clock

generator

CLK2

CLK2C

clk_out

FIFO

phstr sync to NCO

PLL VCO

clk_nco

phase

accumulator

reset

}

DAC5687-EP

SGLS333 – JUNE 2006

Table 12. Synchronization in Different Clock Modes

Clock

PLLVDD

Serial Interface Register Bits

DA, DB,

Description

Mode

PHSTR, and

fifo_bypass

dual_clk

inv_plllock

TXENABLE

Latch

Single

0 V

PLLLOCK

Signal at the PLLLOCK output pin is used to clock the

External

rising edge

PHSTR signal into the chip. The PLLLOCK output

Clock

clock is generated by dividing the CLK2/CLK2C input

PLLLOCK

without

signal by the programmed interpolation and interface

falling edge

FIFO

settings.

Single

0 V

PLLLOCK

Signal at the PLLLOCK output pin is used to clock the

External

rising edge

PHSTR signal into the chip. The PLLLOCK output

Clock with

clock is generated by dividing the CLK2/CLK2C input

PLLLOCK

FIFO

signal by the programmed interpolation and interface

falling edge

settings. Enabling the FIFO allows the chip to function

with large loads on the PLLLOCK output pin at high

input rates. The FIFO must be initialized first in this

mode.

Dual

0 V

CLK1/CLK1C

The CLK1/CLK1C input signal is used to clock in the

External

PHSTR signal. CLK1/CLK1C and CLK2/CLK2C are

Clock

both input to the chip and the phase relationship must

without

be tightly controlled

FIFO

Dual

0 V

CLK1/CLK1C

The CLK1/CLK1C input signal is used to clock in the

External

PHSTR signal. CLK1/CLK1C and CLK2/CLK2C are

Clock with

both input to the chip, but no phase relationship is

FIFO

required. The FIFO input circuits are used to manage

the clock domain transfers. The FIFO must be

initialized in this mode.

PLL

3.3 V

CLK1/CLK1C

The CLK1/CLK1C input signal is used to clock in the

Enabled

PHSTR signal. The FIFO must be bypassed when the

PLL is enabled.

The phase accumulator in the NCO block (see the Fine Mixer (FMIX) section and Figure 40 for a description of

the NCO) can be synchronously reset when PHSTR is asserted. The PHSTR signal passes through the input

FIFO block, using the input clock associated with the clocking mode. If the FIFO is enabled, there can be some

uncertainty in the exact instant the PHSTR synchronization signal arrives at the NCO accumulator due to the

elastic capabilities of the FIFO. For example, in dual-clock mode with the FIFO enabled, the internal clock

generator divides down the CLK2/CLK2C input signal to generate the FIFO output clock. The phase of this

generated clock will be unknown externally, resulting in an uncertainty of the exact PHSTR instant of as much as

a few input clock cycles.

Figure 52. Logic Path for PHSTR Synchronization Signal to NCO

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