R5F10RB8AFP datasheet(16/76 Pages) RENESAS

номер детали	R5F10RB8AFP

подробное описание детали	Integrated LCD controller/driver, True Low Power Platform (as low as 75 關A/MHz, and 0.64 關A for RTC LVD), 1.6 V to 5.5 V operation, 8 to 32 Kbyte Flash, 31 DMIPS at 24 MHz, for All LCD Based Applications

PDF	76 Pages

Scroll/Zoom	100%

производитель	RENESAS [Renesas Technology Corp]

домашняя страница	http://www.renesas.com

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16 / 76 page

RL78/L12

1. OUTLINE

Page 16 of 73

R01DS0157EJ0001 Rev.0.01

2012.02.20

Under development

Preliminary document

Specifications in this document are tentative and subject to change.

(2/2)

32-pin

44-pin

48-pin

52-pin

64-pin

Item

R5F10RBx

R5F10RFx

R5F10RGx

R5F10RJx

R5F10RLx

Clock output/buzzer output

• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz

(Main system clock: fMAIN = 20 MHz operation)

• 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz,

32.768 kHz

(Subsystem clock: fSUB = 32.768 kHz operation)

8/10-bit resolution A/D converter

4 channels

7 channels

9 channels

10 channels

Serial interface

• CSI: 2 channel/UART (LIN-bus supported): 1 channel

2C bus

1 channel

LCD controller/driver

Internal voltage boosting method, capacitor split method, and external resistance

division

method are switchable.

Segment signal output

22 (18)

Note 1

26 (22)

Note 1

30 (26)

Note 1

39 (35)

Note 1

Common signal output

4 (8)

Note 1

Multiplier and

divider/multiply-accumulator

• 16 bits × 16 bits = 32 bits (Unsigned or signed)

• 32 bits ÷ 32 bits = 32 bits (Unsigned)

• 16 bits × 16 bits + 32 bits = 32 bits (Unsigned or signed)

DMA controller

2 channels

Internal

Vectored interrupt

sources

External

Key interrupt

Reset

• Reset by RESET pin

• Internal reset by watchdog timer

• Internal reset by power-on-reset

• Internal reset by voltage detector

• Internal reset by illegal instruction execution Note 2

• Internal reset by RAM parity error

• Internal reset by illegal-memory access

Power-on-reset circuit

• Power-on-reset:

1.51

±0.03 V

• Power-down-reset: 1.50

±0.03 V

Voltage detector

1.63 V to 4.06 V (14 stages)

On-chip debug function

Provided

Power supply voltage

VDD = 1.6 to 5.5 V

Operating ambient temperature

TA =

−40 to +85 °C

Notes 1.

The values in parentheses are the number of signal outputs when 8 com is used.

The illegal instruction is generated when instruction code FFH is executed.

Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or

on-chip debug emulator.

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