R5F10RB8AFP datasheet(37/76 Pages) RENESAS

37 / 76 page

RL78/L12

2. ELECTRICAL SPECIFICATIONS (TARGET)

Page 37 of 73

R01DS0157EJ0001 Rev.0.01

2012.02.20

Under development

Preliminary document

Specifications in this document are tentative and subject to change.

Caution

The pins mounted depend on the product.

Refer to 1.3.1

32-pin products to 1.3.5

64-pin

products.

(2) During communication at same potential (CSI mode) (master mode (fMCK/2, fMCK/4), SCKp... internal

clock output)

(TA =

−40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)

Notes 1. For CSI00, set a cycle of 2/fCLK or longer.

For other than CSI00, set a cycle of 4/fCLK or longer.

2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.

The SIp setup time becomes “to

SCKp

↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.

The SIp hold time becomes “from

SCKp

↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.

The delay time to SOp output

becomes “from SCKp

↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

5. C is the load capacitance of the SCKp and SOp output lines.

Caution

Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and

SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg).

Remarks 1.

p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1),

g: PIM and POM numbers (g = 1)

fMCK: Serial array unit operation clock frequency

(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,

n: Channel number (mn = 00, 01))

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

2.7 V

≤ EVDD ≤ 5.5 V

167

Note 1

2.4 V

≤ EVDD ≤ 5.5 V

250

Note 1

1.8 V

≤ EVDD ≤ 5.5 V

500

Note 1

SCKp cycle time

tKCY1

1.6 V

≤ EVDD ≤ 5.5 V

1000

Note 1

4.0 V

≤ EVDD ≤ 5.5 V

tKCY1/2

− 12

2.7 V

≤ EVDD ≤ 5.5 V

tKCY1/2

− 18

2.4 V

≤ EVDD ≤ 5.5 V

tKCY1/2

− 38

1.8 V

≤ EVDD ≤ 5.5 V

tKCY1/2

− 50

SCKp high-/low-level width

tKH1,

tKL1

1.6 V

≤ EVDD ≤ 5.5 V

tKCY1/2

−

100

4.0 V

≤ EVDD ≤ 5.5 V

2.7 V

≤ EVDD ≤ 5.5 V

2.4 V

≤ EVDD ≤ 5.5 V

1.8 V

≤ EVDD ≤ 5.5 V

110

SIp setup time (to SCKp

↑) Note 2

tSIK1

1.6 V

≤ EVDD ≤ 5.5 V

220

SIp hold time (from SCKp

↑) Note 3

tKSI1

Delay time from SCKp

↓ to

SOp output

Note 4

tKSO1

C = 30 pF

Note 5

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