R5F10RB8AFP datasheet(40/76 Pages) RENESAS

номер детали	R5F10RB8AFP

подробное описание детали	Integrated LCD controller/driver, True Low Power Platform (as low as 75 關A/MHz, and 0.64 關A for RTC LVD), 1.6 V to 5.5 V operation, 8 to 32 Kbyte Flash, 31 DMIPS at 24 MHz, for All LCD Based Applications

PDF	76 Pages

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производитель	RENESAS [Renesas Technology Corp]

домашняя страница	http://www.renesas.com

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40 / 76 page

RL78/L12

2. ELECTRICAL SPECIFICATIONS (TARGET)

Page 40 of 73

R01DS0157EJ0001 Rev.0.01

2012.02.20

Under development

Preliminary document

Specifications in this document are tentative and subject to change.

Caution

The pins mounted depend on the product.

Refer to 1.3.1

32-pin products to 1.3.5

64-pin

products.

(4) Communication at different potential (2.5 V, 3 V) (UART mode) (dedicated baud rate generator output) (1/2)

(TA =

−40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

fMCK/6

Note 1

bps

4.0 V

≤ EVDD ≤ 5.5 V,

2.7 V

≤ Vb ≤ 4.0 V

Theoretical value of the

maximum transfer rate

fCLK = 24 MHz, fMCK = fCLK

4.0

Mbps

fMCK/6

Note 1

bps

2.7 V

≤ EVDD < 4.0 V,

2.3 V

≤ Vb ≤ 2.7 V

Theoretical value of the

maximum transfer rate

fCLK = 24 MHz, fMCK = fCLK

4.0

Mbps

fMCK/6

Notes 1 to 3

bps

Transfer rate

reception

1.8 V

≤ EVDD < 3.3 V,

1.6 V

≤ Vb ≤ 2.0 V

Theoretical value of the

maximum transfer rate

fCLK = 8 MHz, fMCK = fCLK

1.3

Mbps

Notes 1. Transfer rate in the SNOOZE mode : MAX. 9600 bps, MIN. 4800 bps

2. Use it with EVDD

≥Vb.

3. The following conditions are required for low voltage interface when EVDD<VDD.

2.4 V

≤ EVDD < 2.7 V : MAX. 2.6 Mbps

1.8 V

≤ EVDD < 2.4 V : MAX. 1.3 Mbps

1.6 V

≤ EVDD < 1.8 V : MAX. 0.6 Mbps

Caution

Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode

for the TxDq pin by using port input mode register g (PIMg) and port output mode register g

(POMg).

Remarks 1.

Vb[V]: Communication line voltage

q: UART number (q = 0), g: PIM and POM number (g = 1)

3. fMCK: Serial array unit operation clock frequency

(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,

n: Channel number (mn = 00, 01)

4. VIH and VIL below are observation points for the AC characteristics of the serial array unit when

communicating at different potentials in UART mode.

4.0 V

≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V: VIH = 2.2 V, VIL = 0.8 V

2.7 V

≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V: VIH = 2.0 V, VIL = 0.5 V

1.8 V

≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V: VIH = 1.50 V, VIL = 0.32 V

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