R5F10RB8AFP datasheet(38/76 Pages) RENESAS

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RL78/L12

2. ELECTRICAL SPECIFICATIONS (TARGET)

Page 38 of 73

R01DS0157EJ0001 Rev.0.01

2012.02.20

Under development

Preliminary document

Specifications in this document are tentative and subject to change.

Caution

The pins mounted depend on the product.

Refer to 1.3.1

32-pin products to 1.3.5

64-pin

products.

(3) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)

(TA =

−40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

20 MHz < fMCK

8/fMCK

4.0 V

≤ EVDD ≤

5.5 V

fMCK

≤ 20 MHz

6/fMCK

16 MHz < fMCK

8/fMCK

2.7 V

≤ EVDD <

4.0 V

fMCK

≤ 16 MHz

6/fMCK

16 MHz < fMCK

8/fMCK

1.8 V

≤ EVDD <

2.7 V

fMCK

≤ 16 MHz

6/fMCK

SCKp cycle time

Note 5

tKCY2

1.6 V

≤ EVDD < 1.8 V

6/fMCK

SCKp high-/low-level width

tKH2,

tKL2

1.6 V

≤ EVDD ≤ 5.5 V

tKCY2/2

2.7 V

≤ EVDD ≤ 5.5 V

1/fMCK+20

1.8 V

≤ EVDD < 2.7 V

1/fMCK+30

SIp setup time

(to SCKp

↑) Note 1

tSIK2

1.6 V

≤ EVDD < 1.8 V

1/fMCK+40

2.7 V

≤ EVDD ≤ 5.5 V

1/fMCK+31

1.8 V

≤ EVDD < 2.7 V

1/fMCK+31

SIp hold time

(from SCKp

↑) Note 2

tKSI2

1.6 V

≤ EVDD < 1.8 V

1/fMCK+

250

4.0 V

≤ EVDD ≤ 5.5 V

2/fMCK+44

2.7 V

≤ EVDD < 4.0 V

2/fMCK+44

2.4 V

≤ EVDD < 2.7 V

2/fMCK+75

1.8 V

≤ EVDD < 2.4 V

2/fMCK+110

Delay time from SCKp

↓ to

SOp output

Note 3

tKSO2

C = 30 pF

Note 4

1.6 V

≤ EVDD < 1.8 V

2/fMCK+

220

Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.

The SIp setup time becomes “to

SCKp

↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.

The SIp hold time becomes “from

SCKp

↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.

The delay time to SOp output

becomes “from SCKp

↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

4. C is the load capacitance of the SOp output lines.

5. Transfer rate in the SNOOZE mode : MAX. 1 Mbps

Caution

Select the TTL input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp

pin by using port input mode register g (PIMg) and port output mode register g (POMg).

Remarks

1. p: CSI number (p = 00, 01), m: Unit number (m = 0),

n: Channel number (n = 0, 1), g: PIM number (g = 1)

fMCK: Serial array unit operation clock frequency

(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,

n: Channel number (mn = 00, 01))

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