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R5F10RB8AFP датащи(PDF) 34 Page - Renesas Technology Corp

номер детали R5F10RB8AFP
подробное описание детали  Integrated LCD controller/driver, True Low Power Platform (as low as 75 關A/MHz, and 0.64 關A for RTC LVD), 1.6 V to 5.5 V operation, 8 to 32 Kbyte Flash, 31 DMIPS at 24 MHz, for All LCD Based Applications
PDF  76 Pages
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производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R5F10RB8AFP датащи(HTML) 34 Page - Renesas Technology Corp

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RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Page 34 of 73
R01DS0157EJ0001 Rev.0.01
2012.02.20
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
Caution
The pins mounted depend on the product.
Refer to 1.3.1
32-pin products to 1.3.5
64-pin
products.
2.4 AC Characteristics
2.4.1 Basic operation
(TA =
−40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Items
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
2.7 V
≤ VDD ≤ 5.5 V 0.04167
1
μs
High-speed
main mode
2.4 V
≤ VDD < 2.7 V 0.0625
1
μs
Low voltage
main mode
1.6 V
≤ VDD ≤ 5.5 V
0.25
1
μs
Main
system
clock (fMAIN)
operation
Low-speed
main mode
1.8 V
≤ VDD ≤ 5.5 V 0.125
1
μs
Subsystem clock (fSUB)
operation
1.8 V
≤ VDD ≤ 5.5 V
28.5
30.5
31.3
μs
2.7 V
≤ VDD ≤ 5.5 V 0.04167
1
μs
High-speed
main mode
2.4 V
≤ VDD < 2.7 V 0.0625
1
μs
Low voltage
main mode
1.8 V
≤ VDD ≤ 5.5 V
0.25
1
μs
Instruction cycle (minimum
instruction execution time)
TCY
In the self
programming
mode
Low-speed
main mode
1.8 V
≤ VDD ≤ 5.5 V 0.125
1
μs
2.7 V
≤ VDD ≤ 5.5 V
1.0
20.0
MHz
1.8 V
≤ VDD < 2.7 V
1.0
8.0
MHz
fEX
1.6 V
≤ VDD < 1.8 V
1.0
4.0
MHz
External main system clock
frequency
fEXS
32
35
kHz
2.7 V
≤ VDD ≤ 5.5 V
24
ns
1.8 V
≤ VDD < 2.7 V
60
ns
tEXH, tEXL
1.6 V
≤ VDD < 1.8 V
120
ns
External main system clock input
high-level width, low-level width
tEXHS, tEXLS
13.7
μs
TI00 to TI07 input high-level
width, low-level width
tTIH,
tTIL
1/fMCK+10
ns
Note
4.0 V
≤ EVDD ≤ 5.5 V
12
MHz
2.7 V
≤ EVDD < 4.0 V
8
MHz
1.8 V
≤ EVDD < 2.7 V
4
MHz
High-speed main
mode
1.6 V
≤ EVDD < 1.8 V
2
MHz
Low voltage main
mode
1.6 V
≤ EVDD ≤ 5.5 V
2
MHz
1.8 V
≤ EVDD ≤ 5.5 V
4
MHz
TO00 to TO07 output frequency
fTO
Low-speed main
mode
1.6 V
≤ EVDD < 1.8 V
2
MHz
4.0 V
≤ EVDD ≤ 5.5 V
16
MHz
2.7 V
≤ EVDD < 4.0 V
8
MHz
1.8 V
≤ EVDD < 2.7 V
4
MHz
High-speed main
mode
1.6 V
≤ EVDD < 1.8 V
2
MHz
1.8 V
≤ EVDD ≤ 5.5 V
4
MHz
Low voltage main
mode
1.6 V
≤ EVDD < 1.8 V
2
MHz
1.8 V
≤ EVDD ≤ 5.5 V
4
MHz
PCLBUZ0, PCLBUZ1 output
frequency
fPCL
Low-speed main
mode
1.6 V
≤ EVDD < 1.8 V
2
MHz
INTP0
1.6 V
≤ VDD ≤ 5.5 V
1
μs
Interrupt input high-level width,
low-level width
tINTH,
tINTL
INTP1 to INTP7
1.6 V
≤ EVDD ≤ 5.5 V
1
μs
1.8 V
≤ EVDD ≤ 5.5 V
250
ns
Key interrupt input low-level width tKR
KR0 to KR3
1.6 V
≤ EVDD < 1.8 V
1
μs
RESET low-level width
tRSL
10
μs
(Note and Remark are listed on the next page.)



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