LPC4350 datasheet(116/145 Pages) NXP

номер детали	LPC4350

подробное описание детали	32-bit ARM Cortex-M4/M0 MCU; up to 264 kB SRAM; Ethernet two High-speed USBs; advanced configurable peripherals

PDF	145 Pages

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производитель	NXP [NXP Semiconductors]

домашняя страница	http://www.nxp.com

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116 / 145 page

LPC4350_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 2.1 — 23 September 2011

116 of 145

NXP Semiconductors

LPC4350/30/20/10

32-bit ARM Cortex-M4/M0 microcontroller

11.9 Ethernet

Fig 36. Dynamic external memory interface signal timing (read access)

002aag205

td(CS)

Tcy(clk)

th(CS)

td(RAS)

td(A)

td(CAS)

td(DQM)

tsu(D)

th(D)

th(RAS)

th(CAS)

th(A)

th(DQM)

EMC_CLKx

EMC_DYCSx

EMC_RAS

EMC_CAS

EMC_WE

EMC_DQMOUTx

EMC_Ax

EMC_Dx

Table 20.

Dynamic characteristics: Ethernet

Tamb = 40 C to 85 C, VDD(REG)(3V3) = <tbd>.

Symbol Parameter

Conditions

Min

Max

Unit

RMII mode

fclk

clock frequency

for ENET_RX_CLK

[1]

<tbd>

MHz



clk

clock duty cycle

[1]

<tbd>

tsu

set-up time

for ENET_TXDn, ENET_TX_EN,

ENET_RXDn, ENET_RX_ER,

ENET_RX_DV

[1][2]

<tbd>

hold time

for ENET_TXDn, ENET_TX_EN,

ENET_RXDn, ENET_RX_ER,

ENET_RX_DV

[1][2]

<tbd>

MII mode

fclk

clock frequency

for ENET_TX_CLK

[1]

<tbd>

MHz



clk

clock duty cycle

[1]

<tbd>

tsu

set-up time

for ENET_TXDn, ENET_TX_EN,

ENET_TX_ER

[1][2]

<tbd>

hold time

for ENET_TXDn, ENET_TX_EN,

ENET_TX_ER

[1][2]

<tbd>

fclk

clock frequency

for ENET_RX_CLK

[1]

<tbd>

MHz

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