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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LPC4350 датащи(PDF) 112 Page - NXP Semiconductors |
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LPC4350 датащи(HTML) 112 Page - NXP Semiconductors |
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112 / 145 page  LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2.1 — 23 September 2011 112 of 145 NXP Semiconductors LPC4350/30/20/10 32-bit ARM Cortex-M4/M0 microcontroller 11.8 External memory interface Table 17. Dynamic characteristics: Static external memory interface CL =30 pF, Tamb = 40 C to 85 C, VDD(REG)(3V3) = <tbd>. Symbol Parameter[1] Conditions[1] Min Typ Max Unit Read cycle parameters[2] tCSLAV CS LOW to address valid time RD1 <tbd> <tbd> <tbd> ns tCSLOEL CS LOW to OE LOW time RD2 <tbd> + Tcy(clk) WAITOEN <tbd> + Tcy(clk) WAITOEN <tbd> + Tcy(clk) WAITOEN ns tCSLBLSL CS LOW to BLS LOW time RD3; PB = 1 <tbd> <tbd> <tbd> ns tOELOEH OE LOW to OE HIGH time RD4 (WAITRD WAITOEN + 1) Tcy(clk) <tbd> (WAITRD WAITOEN + 1) Tcy(clk) <tbd> (WAITRD WAITOEN + 1) Tcy(clk) <tbd> ns tam memory access time RD5 [3] (WAITRD WAITOEN +1) Tcy(clk) <tbd> (WAITRD WAITOEN +1) Tcy(clk) <tbd> (WAITRD WAITOEN +1) Tcy(clk) <tbd> ns th(D) data input hold time RD6 [4] <tbd> <tbd> <tbd> ns tCSHBLSH CS HIGH to BLS HIGH time PB = 1 <tbd> <tbd> <tbd> ns tCSHOEH CS HIGH to OE HIGH time <tbd> <tbd> <tbd> ns tOEHANV OE HIGH to address invalid time <tbd> <tbd> <tbd> ns tdeact deactivation time RD7 <tbd> <tbd> <tbd> ns Write cycle parameters[2] tCSLAV CS LOW to address valid time WR1 <tbd> <tbd> <tbd> ns tCSLDV CS LOW to data valid time WR2 <tbd> <tbd> <tbd> ns tCSLWEL CS LOW to WE LOW time WR3; PB =1 <tbd> + Tcy(clk) (1 + WAITWEN) <tbd> + Tcy(clk) (1 + WAITWEN) <tbd> + Tcy(clk) (1 + WAITWEN) ns tCSLBLSL CS LOW to BLS LOW time WR4; PB = 1 <tbd> <tbd> <tbd> ns tWELWEH WE LOW to WE HIGH time WR5; PB =1 (WAITWR WAITWEN + 1) Tcy(clk) <tbd> (WAITWR WAITWEN + 1) Tcy(clk) <tbd> (WAITWR WAITWEN + 1) Tcy(clk) <tbd> ns tBLSLBLSH BLS LOW to BLS HIGH time PB = 1 (WAITWR WAITWEN + 3) Tcy(clk) <tbd> (WAITWR WAITWEN + 3) Tcy(clk) <tbd> (WAITWR WAITWEN + 3) Tcy(clk) <tbd> ns tWEHDNV WE HIGH to data invalid time WR6; PB =1 <tbd> + Tcy(clk) <tbd> + Tcy(clk) <tbd> + Tcy(clk) ns tWEHEOW WE HIGH to end of write time WR7; PB = 1 [5] <tbd> + Tcy(clk) <tbd> + Tcy(clk) <tbd> + Tcy(clk) ns tBLSHDNV BLS HIGH to data invalid time PB = 1 <tbd> <tbd> <tbd> ns tWEHANV WE HIGH to address invalid time PB = 1 <tbd> + Tcy(clk) <tbd> + Tcy(clk) <tbd> + Tcy(clk) ns tdeact deactivation time WR8; PB = 0; PB = 1 <tbd> <tbd> <tbd> ns tCSLBLSL CS LOW to BLS LOW WR9; PB = 0 <tbd> <tbd> <tbd> ns |
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