LPC4350 datasheet(77/145 Pages) NXP

77 / 145 page

LPC4350_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 2.1 — 23 September 2011

77 of 145

NXP Semiconductors

LPC4350/30/20/10

32-bit ARM Cortex-M4/M0 microcontroller

• This module has its own, integrated DMA engine.

• USB interface electrical test software included in ROM USB stack.

7.17.6 High-speed USB Host/Device interface with ULPI (USB1)

Remark: The USB1 controller is available on parts LPC4350/30. See Table 2.

The USB1 interface can operate as a full-speed USB Host/Device interface or can

connect to an external ULPI PHY for High-speed operation.

7.17.6.1

Features

• Complies with Universal Serial Bus specification 2.0.

• Complies with Enhanced Host Controller Interface Specification.

• Supports auto USB 2.0 mode discovery.

• Supports all high-speed USB-compliant peripherals if connected to external ULPI

PHY.

• Supports all full-speed USB-compliant peripherals.

• Supports interrupts.

• This module has its own, integrated DMA engine.

• USB interface electrical test software included in ROM USB stack.

7.17.7 LCD controller

Remark: The LCD controller is available on the LPC4350 parts. See Table 2.

The LCD controller provides all of the necessary control signals to interface directly to a

variety of color and monochrome LCD panels. Both STN (single and dual panel) and TFT

panels can be operated. The display resolution is selectable and can be up to 1024

 768

pixels. Several color modes are provided, up to a 24-bit true-color non-palettized mode.

An on-chip 512-byte color palette allows reducing bus utilization (i.e. memory size of the

displayed data) while still supporting a large number of colors.

The LCD interface includes its own DMA controller to allow it to operate independently of

the CPU and other system functions. A built-in FIFO acts as a buffer for display data,

providing flexibility for system timing. Hardware cursor support can further reduce the

amount of CPU time needed to operate the display.

7.17.7.1

Features

• AHB master interface to access frame buffer.

• Setup and control via a separate AHB slave interface.

• Dual 16-deep programmable 64-bit wide FIFOs for buffering incoming display data.

• Supports single and dual-panel monochrome Super Twisted Nematic (STN) displays

with 4-bit or 8-bit interfaces.

• Supports single and dual-panel color STN displays.

• Supports Thin Film Transistor (TFT) color displays.

• Programmable display resolution including, but not limited to: 320  200, 320  240,

640

 200, 640  240, 640  480, 800  600, and 1024  768.

• Hardware cursor support for single-panel displays.

LPC4350 датащи(PDF) 77 Page - NXP Semiconductors

LPC4350 датащи(HTML) 77 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL