LPC4350 datasheet(65/145 Pages) NXP

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LPC4350_30_20_10

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Objective data sheet

Rev. 2.1 — 23 September 2011

65 of 145

NXP Semiconductors

LPC4350/30/20/10

32-bit ARM Cortex-M4/M0 microcontroller

Functional description

7.1 Architectural overview

The ARM Cortex-M4 includes three AHB-Lite buses: the system bus, the I-code bus, and

the D-code bus. The I-code and D-code core buses allow for concurrent code and data

accesses from different slave ports.

The LPC4350/30/20/10 use a multi-layer AHB matrix to connect the ARM Cortex-M4

buses and other bus masters to peripherals in a flexible manner that optimizes

performance by allowing peripherals that are on different slaves ports of the matrix to be

accessed simultaneously by different bus masters.

An ARM Cortex-M0 co-processor is included in the LPC4350/30/20/10, capable of

off-loading the main ARM Cortex-M4 application processor. Most peripheral interrupts are

connected to both processors. The processors communicate with each other via an

interprocessor communication protocol.

7.2 ARM Cortex-M4 processor

The ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture

with separate local instruction and data buses as well as a third bus for peripherals, and

includes an internal prefetch unit that supports speculative branching. The ARM

Cortex-M4 supports single-cycle digital signal processing and SIMD instructions. A

hardware floating-point processor is integrated in the core. The processor includes a

NVIC with up to 53 interrupts.

7.3 ARM Cortex-M0 co-processor

The ARM Cortex-M0 is a general purpose, 32-bit microprocessor, which offers high

performance and very low power consumption. The ARM Cortex-M0 co-processor uses a

3-stage pipeline von Neumann architecture and a small but powerful instruction set

providing high-end processing hardware. The co-processor incorporates a NVIC with 32

interrupts.

7.4 Interprocessor communication

The ARM Cortex-M4 and ARM Cortex-M0 interprocessor communication is based on

using shared SRAM as mailbox and one processor raising an interrupt on the other

processor's NVIC, for example after it has delivered a new message in the mailbox. The

receiving processor can reply by raising an interrupt on the sending processor's NVIC to

acknowledge the message.

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