LPC4350 datasheet(79/145 Pages) NXP

79 / 145 page

LPC4350_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 2.1 — 23 September 2011

79 of 145

NXP Semiconductors

LPC4350/30/20/10

32-bit ARM Cortex-M4/M0 microcontroller

7.18.1.1

Features

• Maximum UART data bit rate of <tbd> MBit/s.

• 16 B Receive and Transmit FIFOs.

• Register locations conform to 16C550 industry standard.

• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.

• Built-in fractional baud rate generator covering wide range of baud rates without a

need for external crystals of particular values.

• Auto baud capabilities and FIFO control mechanism that enables software flow

control implementation.

• Equipped with standard modem interface signals. This module also provides full

support for hardware flow control.

• Support for RS-485/9-bit/EIA-485 mode (UART1).

• DMA support.

7.18.2 USART0/2/3

The LPC4350/30/20/10 contain three USARTs. In addition to standard transmit and

receive data lines, the USARTs support a synchronous mode.

The USARTs include a fractional baud rate generator. Standard baud rates such as

115200 Bd can be achieved with any crystal frequency above 2 MHz.

7.18.2.1

Features

• Maximum UART data bit rate of <tbd> MBit/s.

• 16 B Receive and Transmit FIFOs.

• Register locations conform to 16C550 industry standard.

• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.

• Built-in fractional baud rate generator covering wide range of baud rates without a

need for external crystals of particular values.

• Auto baud capabilities and FIFO control mechanism that enables software flow

control implementation.

• Support for RS-485/9-bit/EIA-485 mode.

• USART3 includes an IrDA mode to support infrared communication.

• All USARTs have DMA support.

• Support for synchronous mode.

• Smart card mode conforming to ISO7816 specification

7.18.3 SPI serial I/O controller

The LPC4350/30/20/10 contain one SPI controller. SPI is a full duplex serial interface

designed to handle multiple masters and slaves connected to a given bus. Only a single

master and a single slave can communicate on the interface during a given data transfer.

During a data transfer the master always sends 8 bits to 16 bits of data to the slave, and

the slave always sends 8 bits to 16 bits of data to the master.

LPC4350 датащи(PDF) 79 Page - NXP Semiconductors

LPC4350 датащи(HTML) 79 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL