LPC4350 datasheet(64/145 Pages) NXP

64 / 145 page

LPC4350_30_20_10

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Objective data sheet

Rev. 2.1 — 23 September 2011

64 of 145

NXP Semiconductors

LPC4350/30/20/10

32-bit ARM Cortex-M4/M0 microcontroller

[5]

5 V tolerant pad with 15 ns glitch filter providing high-speed digital I/O functions with TTL levels and hysteresis.

[6]

5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input or output. When configured as a ADC

input or DAC output, the pin is not 5 V tolerant and the digital section of the pad must be disabled by setting the pin to an input function

and disabling the pull-up resistor through the pin’s SFSP register.

[7]

5 V tolerant transparent analog pad.

[8]

Transparent analog pad. Not 5 V tolerant.

[9]

Pad provides USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode

only). This pad is not 5 V tolerant.

[10] Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus 400 kHz specification. This pad requires an external pull-up to provide

output functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines.

Open-drain configuration applies to all functions on this pin.

[11] 5 V tolerant pad with 20 ns glitch filter; provides digital I/O functions with open-drain output with weak pull-up resistor and hysteresis.

[12] On the TFBGA100 and LQFP208 packages, VPP is internally connected to VDDIO.

[13] On the LQFP144 package, VSSIO and VSS are connected to a common ground plane.

[14] On the TFBGA100 and LQFP100/208 packages, VSS is internally connected to VSSIO.

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