PIC32MX795F512LT-80ISLASHPF datasheet(239/256 Pages) MICROCHIP

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DS61156G-page 239

PIC32MX5XX/6XX/7XX

APPENDIX A: MIGRATING FROM

PIC32MX3XX/4XX TO

PIC32MX5XX/6XX/7XX

DEVICES

This appendix provides an overview of considerations

for migrating from PIC32MX3XX/4XX devices to the

PIC32MX5XX/6XX/7XX family of devices. The code

developed for the PIC32MX3XX/4XX devices can be

ported to the PIC32MX5XX/6XX/7XX devices after

making the appropriate changes outlined below.

A.1

DMA

PIC32MX5XX/6XX/7XX devices do not support

stopping DMA transfers in Idle mode.

A.2

Interrupts

PIC32MX5XX/6XX/7XX

devices

have

persistent

interrupts for some of the peripheral modules. This

means that the interrupt condition for these peripherals

must be cleared before the interrupt flag can be

cleared.

For example, to clear a UART receive interrupt, the

user application must first read the UART Receive

the associated UxIF flag to clear the pending UART

interrupt. In other words, the UxIF flag cannot be

cleared by software until the UART Receive register is

read.

Table A-1 outlines the peripherals and associated

interrupts

that are

implemented

differently

PIC32MX5XX/6XX/7XX

versus

PIC32MX3XX/4XX

devices.

In addition, on the SPI module, the IRQ numbers for the

receive done interrupts were changed from 25 to 24

and the transfer done interrupts were changed from 24

to 25.

TABLE A-1:

PIC32MX3XX/4XX VERSUS PIC32MX5XX/6XX/7XX INTERRUPT IMPLEMENTATION

DIFFERENCES

Module

Interrupt Implementation

Input Capture

To clear an interrupt source, read the Buffer Result (ICxBUF) register to obtain the number of

capture results in the buffer that are below the interrupt threshold (specified by ICI<1:0> bits).

SPI

Receive and transmit interrupts are controlled by the SRXISEL<1:0> and STXISEL<1:0> bits,

respectively. To clear an interrupt source, data must be written to, or read from, the SPIxBUF

SRXISEL<1:0> and STXISEL<1:0> bits.

UART

TX interrupt will be generated as soon as the UART module is enabled.

Receive and transmit interrupts are controlled by the URXISEL<1:0> and UTXISEL<1:0> bits,

respectively. To clear an interrupt source, data must be read from, or written to, the UxRXREG or

UxTXREG registers to obtain the number of data to receive/transmit below the level specified by

the URXISEL<1:0> and UTXISEL<1:0> bits.

ADC

All samples must be read from the result registers (ADC1BUFx) to clear the interrupt source.

PMP

To clear an interrupt source, read the Parallel Master Port Data Input/Output (PMDIN/PMDOUT)

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