MCP4716 datasheet(71/86 Pages) MICROCHIP

71 / 86 page

DS22272A-page 71

MCP4706/4716/4726

8.10

Design Considerations

In the design of a system with the MCP4706/4716/4726

devices, the following considerations should be taken

into account:

• Power Supply Considerations

• Layout Considerations

8.10.1

POWER SUPPLY

CONSIDERATIONS

The typical application will require a bypass capacitor

in order to filter high-frequency noise, which can be

induced onto the power supply's traces. The bypass

capacitor helps to minimize the effect of these noise

sources on signal integrity. Figure 8-10 illustrates an

appropriate bypass strategy.

In this example, the recommended bypass capacitor

value is 0.1 µF. This capacitor should be placed as

close (within 4 mm) to the device power pin (VDD) as

possible.

The power source supplying these devices should be

as clean as possible. If the application circuit has

separate digital and analog power supplies, VDD and

VSS should reside on the analog plane.

FIGURE 8-10:

Typical Microcontroller

Connections.

8.10.2

LAYOUT CONSIDERATIONS

Several layout considerations may be applicable to

your application. These may include:

• Noise

• PCB Area Requirements

8.10.2.1

Noise

Inductively-coupled AC transients and digital switching

noise can degrade the input and output signal integrity,

potentially masking the MCP47X6’s performance.

Careful board layout minimizes these effects and

increases the Signal-to-Noise Ratio (SNR). Multi-layer

boards

utilizing a low-inductance ground plane,

isolated inputs, isolated outputs and proper decoupling

are critical to achieving the performance that the silicon

capable

providing.

Particularly

harsh

environments may require shielding of critical signals.

Separate digital and analog ground planes are

recommended. In this case, the VSS pin and the ground

pins of the VDD capacitors should be terminated to the

analog ground plane.

8.10.2.2

PCB Area Requirements

In some applications, PCB area is a criteria for device

selection.

Table 8-2

shows

the

typical

package

dimensions and area for the different package options.

The table also shows the relative area factor compared

to the smallest area. For space critical applications, the

DFN package would be the suggested package.

TABLE 8-2:

PACKAGE FOOTPRINT (1)

VDD

VSS

0.1 µF

SCL

VOUT

VREF

SDA

Note:

Breadboards and wire-wrapped boards

are not recommended.

Package

Package Footprint

Type

Code

Dimensions

(mm)

Length Width

SOT-23

2.90

2.70

7.83

1.96

DFN

2.00

4.00

Note 1: Does not include recommended land

pattern

dimensions.

Dimensions

are

typical values.

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