MCP4716 datasheet(40/86 Pages) MICROCHIP

40 / 86 page

MCP4706/4716/4726

DS22272A-page 40

4.6

Device Resets

Device Resets can be grouped into two types. Resets

due to change in voltage (POR/BOR Reset), and resets

caused

the

system

master

(such

microcontroller).

After a device reset, and when VDD ≥ VDD(MIN), the

device memory may be written or read.

4.6.1

POR/BOR RESET OPERATION

The POR and BOR trip points are at the same voltage,

and is determined if the VDD voltage is rising or falling

(see Figure 4-1). What occurs is different depending if

the reset is a POR or BOR reset.

POR Reset (VDD Rising)

On a POR Reset, the nonvolatile memory values (DAC

volatile memory. This configures the analog output

(VOUT) circuitry. Also a reset delay timer starts. During

this delay time, the I2C interface will not accept

commands.

BOR Reset (VDD Falling)

On a BOR Reset, the device is forced into a power

down state. The volatile PD1:PD0 bits forced to ‘11’ and

all other volatile memory forced to ‘0’. The I2C interface

will not accept commands.

4.6.2

RESET COMMANDS

When the MCP47X6 is in the valid operating voltage,

the I2C General Call Reset command will force a reset

event. This is similar to the POR reset, except that the

reset delay timer is not started.

In the case where the I2C Interface bus does not seem

to be responsive, the technique shown in Section 8.9,

Software I2C Interface Reset Sequence can be used

to force the I2C interface to be reset.

4.7

DAC Registers, Configuration

Bits, and Status Bits

The MCP47X6 devices have both volatile and

nonvolatile (EEPROM) memory. Figure 4-6 shows the

volatile and nonvolatile memory and their interaction

due to a POR event.

There are five configuration bits in both the volatile and

nonvolatile memory, the DAC registers in both the

volatile and nonvolatile memory, and two volatile status

bits. The DAC registers (volatile and nonvolatile) will be

either 12-bits (MCP4726), 10-bits (MCP4716), or 8-bits

(MCP4706) wide.

When the device is first powered up, it automatically

uploads the EEPROM memory values to the volatile

memory. The volatile memory determines the analog

output (VOUT) pin voltage. After the device is powered

up, the user can update the device memory.

The I2C interface is how this memory is read and

written. Refer to Section 5.0 “I2C Serial Interface”

and Section 6.0 “MCP47X6 I2C Commands” for

more details on the reading and writing the device’s

memory.

When the nonvolatile memory is written (using the I2C

Write All Memory command), the volatile memory is

written with the same values. The device starts writing

the EEPROM cell at the acknowledge pulse of the

EEPROM write command.

Table 4-3 shows the operation of the device status bits,

Table 4-4

shows

the

operation

the

device

configuration bits, and Table 4-5 shows the factory

default value of a POR/BOR event for the device

configuration bits.

There are two Status bits. These are only in volatile

memory and give indication on the status of the device.

The POR bit indicates if the device VDD is above or

below the POR trip point. During normal operation, this

bit should be ‘1’. The RDY/BSY bit indicates if an

EEPROM write cycle is in progress. While the RDY/

BSY bit is low (during the EEPROM writing), all

commands are ignored, except for the Read Command

command.

FIGURE 4-6:

DAC Memory and POR Interaction.

VREF1

DAC Register Value (1)

N.V. Memory

Config Bits

Vol. Memory

POR Event

VREF0

PD1

PD0

VREF1 VREF0

PD1

PD0

RDY/BSY

POR

Status Bits (2)

DMAX

Note 1: The DMAX value depends on the device. For the MCP4706: DMAX = D7, MCP4716: DMAX = D9,

and the MCP4726: DMAX = D11.

2: Status bits are read only

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