MCP4716 datasheet(47/86 Pages) MICROCHIP

47 / 86 page

DS22272A-page 47

MCP4706/4716/4726

5.3.6

HS MODE

The I2C specification requires that a high-speed mode

device must be ‘activated’ to operate in high-speed

(3.4 Mbit/s) mode. This is done by the Master sending

a special address byte following the START bit. This

byte is referred to as the high-speed Master Mode

Code (HSMMC).

The MCP47X6 device does not acknowledge this byte.

However, upon receiving this command, the device

switches

mode.

The

device

can

now

communicate at up to 3.4 Mbit/s on SDA and SCL

lines. The device will switch out of the HS mode on the

next STOP condition.

The master code is sent as follows:

START condition (S)

High-Speed Master Mode Code (0000 1XXX),

The XXX bits are unique to the high-speed (HS)

mode Master.

No Acknowledge (A)

After switching to the High-Speed mode, the next

transferred byte is the I2C control byte, which specifies

the device to communicate with, and any number of

data bytes plus acknowledgements. The Master

Device can then either issue a Repeated Start bit to

address a different device (at High-Speed) or a Stop bit

to return to Fast/Standard bus speed. After the Stop bit,

any other Master Device (in a Multi-Master system) can

arbitrate for the I2C bus.

See Figure 5-10 for illustration of HS mode command

sequence.

For more information on the HS mode, or other I2C

modes, please refer to the NXP I2C specification.

5.3.6.1

Slope Control

The slope control on the SDA output is different

between the Fast/Standard Speed and the High-Speed

clock modes of the interface.

5.3.6.2

Pulse Gobbler

The pulse gobbler on the SCL pin is automatically

adjusted to suppress spikes < 10 ns during HS mode.

FIGURE 5-10:

HS Mode Sequence.

‘0 0 0 0 1 X X X’b

‘Slave Address’

A/A

“Data”

S = Start bit

Sr = Repeated Start bit

A = Acknowledge bit

A = Not Acknowledge bit

R/W = Read/Write bit

R/W

P = Stop bit (Stop condition terminates HS Mode)

F/S-mode

HS-mode

HS-mode continues

F/S-mode

‘Slave Address’ R/W

HS Select Byte

Control Byte

Command/Data Byte(s)

Control Byte

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