MCP4716 datasheet(37/86 Pages) MICROCHIP

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DS22272A-page 37

MCP4706/4716/4726

4.4

Output Buffer / VOUT Operation

The DAC output is buffered with a low power and

precision output amplifier (op amp). Figure 4-4 shows

a block diagram.

This amplifier provides a rail-to-rail output with low

offset voltage and low noise. The user can select the

output gain of the output amplifier. Gain options are:

Gain of 1, with either VDD or VREF pin used as

reference voltage

Gain of 2, only when VREF pin is used as

reference voltage. The VREF pin voltage should

be limited to VDD/2.

The amplifier’s output can drive the resistive and high

capacitive loads without oscillation. The amplifier

provides a maximum load current which is enough for

most programmable voltage reference applications.

Refer to Section 1.0 “Electrical Characteristics” for

the specifications of the output amplifier.

In any of the three Power-Down modes, the op amp is

powered down and it’s output becomes a high

impedance to the VOUT pin.

FIGURE 4-4:

Output Buffer Block

Diagram.

4.4.1

PROGRAMMABLE GAIN

The amplifier’s gain is controlled by the Gain (G)

configuration bit (See Table 4-4) and the VRL reference

selection. When the VRL reference selection is the

device’s VDD voltage, the G bit is ignored and a gain of

1 is used. The volatile G bit value can be modified by:

• POR event

• BOR event

•I2C write commands

•I2C General Call Reset command

4.4.2

OUTPUT VOLTAGE

The volatile DAC Register’s value controls the analog

VOUT voltage, along with the device’s five configuration

bits. The volatile DAC Register’s value is unsigned

binary.

The formula for the output voltage is given in

Equation 4-1. Table 4-1 shows examples of volatile

DAC Register values and the corresponding theoretical

VOUT voltage for the MCP47X6 devices.

EQUATION 4-1:

CALCULATING OUTPUT

VOLTAGE (VOUT)

The DAC register value will be latched on the falling

edge of the acknowledge pulse of the write command’s

last byte. Then the VOUT voltage will start driving to the

new value.

The following events update the analog voltage output

(VOUT):

• Power-On-Reset or General Call Reset

command: Output is updated with EEPROM data.

• Falling edge of the acknowledge pulse of the last

write command byte.

4.4.2.1

Resolution / Step Voltage

The Step voltage is dependent on the device resolution

and the output voltage range. One LSb is defined as

the ideal voltage difference between two successive

codes. The step voltage can easily be calculated by

using Equation 4-1 where the DAC Register Value is

equal to 1.

4.4.3

DRIVING RESISTIVE AND

CAPACITIVE LOADS

The VOUT pin can drive up to 100 pF of capacitive load

in parallel with a 5 k

Ω resistive load (to meet electrical

specifications). Figure 2-57 shows the VOUT vs.

Resistive Load.

VOUT drops slowly as the load resistance decreases

after about 3.5 k

Ω. It is recommended to use a load

with RL greater than 5 kΩ.

Note:

The load resistance must keep higher

than 5 k

Ω for the stable and expected

analog

output

(to

meet

electrical

specifications).

VOUT

Amp

Gain (1x or 2x)

(G = 0 or 1)

Note:

When Gain = 2 (VRL = VREF),

if VREF > VDD / 2, the VOUT voltage will be

limited to VDD. So if VREF = VDD, then the

VOUT voltage will not change for volatile

DAC Register

values

mid-scale

and

greater, since the op amp at full scale

output.

VOUT =

* Gain

VRL * DAC Register Value

# Resistors in Resistor Ladder

# Resistors in Resistor Ladder = 4096 (MCP4726)

1024 (MCP4716)

256 (MCP4706)

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