MCP4716 datasheet(36/86 Pages) MICROCHIP

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MCP4706/4716/4726

DS22272A-page 36

4.2

DAC’s (Resistor Ladder)

Reference Voltage

The device can be configured to use one of three

voltage sources for the resistor ladder’s reference

voltage (VRL) (see Figure 4-2). These are:

VDD pin voltage

VREF pin voltage internally buffered

VREF pin voltage unbuffered

The selection of the voltage is specified with the volatile

VREF1:VREF0 configuration bits (see Table 4-4). There

are nonvolatile and volatile VREF1:VREF0 configuration

bits. On a POR/BOR event, the state of the nonvolatile

VREF1:VREF0 configuration bits are latched into the

volatile VREF1:VREF0 configuration bits.

When the user selects the VDD as reference, the VREF

pin voltage is not connected to the resistor ladder.

If the VREF pin is selected, then one needs to select

between the buffered or unbuffered mode.

In unbuffered mode, the VREF pin voltage may be from

VSS to VDD.

In buffered mode, the VREF pin voltage may be from

0.01V to VDD-0.04V. The input buffer (amplifier)

provides low offset voltage, low noise, and a very high

input impedance, with only minor limitations on the

input range and frequency response.

FIGURE 4-2:

Resistor Ladder Reference

Voltage Selection Block Diagram.

4.3

Resistor Ladder

The resistor ladder is a digital potentiometer with the B

Terminal internally grounded and the A terminal

connected to the selected reference voltage (see

Figure 4-3). The volatile DAC register controls the

wiper position. The wiper voltage (VW) is proportional to

the DAC register value divided by the number of

resistor elements (RS) in the ladder (256, 1024, or

4096) related to the VRL voltage.

The resistor ladder (RRL) has a typical impedance of

approximately 210 k

Ω. This resistor ladder resistance

(RRL) may vary from device to device up to ±20%.

Since this is a voltage divider configuration, the actual

RRL resistance does not effect the output given a fixed

voltage at VRL.

If the unbuffered VREF pin is used as the VRL voltage

source, this voltage source should have a low output

impedance.

When the DAC is powered down, the resistor ladder is

disconnected from the selected reference voltage.

FIGURE 4-3:

Resistor Ladder.

Note:

In unbuffered mode, the voltage source

should have a low output impedance. If

the voltage source has a high output

impedance, then the voltage on the

VREF’s pin would be lower than expected.

The

resistor

ladder

has

typical

impedance of 210 k

Ω and a typical

capacitance of 29 pF.

Note:

Any variation or noises on the reference

source can directly affect the DAC output.

The reference voltage needs to be as

clean as possible for accurate DAC

performance.

VRL

VDD

Buffer

VREF1:VREF0

VREF

Note:

The maximum wiper position is 2n - 1,

while the number of resistors in the

resistor ladder is 2n. This means that

when the DAC register is at full scale,

there

one

resistor

element

(RS)

between the wiper and the VRL voltage.

RS(2n)

RS(2n - 1)

RS(2n - 2)

RS(1)

2n - 1

2n - 2

RRL

VRL

DAC

VW =

* VRL

DAC Register Value

# Resistors in Resistor Ladder

Where:

# Resistors in Resistor Ladder = 256 (MCP4706)

1024 (MCP4716)

4096 (MCP4726)

PD1:PD0

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