DSPIC30F2010 datasheet(116/202 Pages) MICROCHIP

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dsPIC30F2010

DS70118J-page 116

18.7.1

1 Msps CONFIGURATION

GUIDELINE

The configuration for 1 Msps operation is dependent on

whether a single input pin is to be sampled or whether

multiple pins will be sampled.

18.7.1.1

Single Analog Input

For conversions at 1 Msps for a single analog input, at

least two sample and hold channels must be enabled.

The analog input multiplexer must be configured so

that the same input pin is connected to both sample

and hold channels. The A/D converts the value held on

one S/H channel, while the second S/H channel

acquires a new input sample.

18.7.1.2

Multiple Analog Inputs

The A/D converter can also be used to sample multiple

analog inputs using multiple sample and hold channels.

In this case, the total 1 Msps conversion rate is divided

among the different input signals. For example, four

inputs can be sampled at a rate of 250 ksps for each

signal or two inputs could be sampled at a rate of

500 ksps for each signal. Sequential sampling must be

used in this configuration to allow adequate sampling

time on each input.

18.7.1.3

1 Msps Configuration Items

The following configuration items are required to

achieve a 1 Msps conversion rate.

• Comply with conditions provided in Table 19-2

• Connect external VREF+ and VREF- pins following

the recommended circuit shown in Figure 18-2

• Set SSRC<2:0> = 111 in the ADCON1 register to

enable the auto-convert option

• Enable automatic sampling by setting the ASAM

control bit in the ADCON1 register

• Enable sequential sampling by clearing the

SIMSAM bit in the ADCON1 register

• Enable at least two sample and hold channels by

writing the CHPS<1:0> control bits in the

ADCON2 register

• Write the SMPI<3:0> control bits in the ADCON2

between interrupts. At a minimum, set

SMPI<3:0> = 0001 since at least two sample and

hold channels should be enabled

• Configure the A/D clock period to be:

by writing to the ADCS<5:0> control bits in the

ADCON3 register

• Configure the sampling time to be 2 TAD by

writing: SAMC<4:0> = 00010

• Select at least two channels per analog input pin

by writing to the ADCHS register

18.7.2

750 ksps CONFIGURATION

GUIDELINE

The following configuration items are required to

achieve a 750 ksps conversion rate. This configuration

assumes that a single analog input is to be sampled.

• Comply with conditions provided in Table 18-2

• Connect external VREF+ and VREF- pins following

the recommended circuit shown in Figure 18-2

• Set SSRC<2:0> = 111 in the ADCON1 register to

enable the auto-convert option

• Enable automatic sampling by setting the ASAM

control bit in the ADCON1 register

• Enable one sample and hold channel by setting

CHPS<1:0> = 00 in the ADCON2 register

• Write the SMPI<3:0> control bits in the ADCON2

between interrupts

• Configure the A/D clock period to be:

by writing to the ADCS<5:0> control bits in the

ADCON3 register

• Configure the sampling time to be 2 TAD by

writing: SAMC<4:0> = 00010

18.7.3

600 ksps CONFIGURATION

GUIDELINE

The configuration for 600 ksps operation is dependent

on whether a single input pin is to be sampled or

whether multiple pins will be sampled.

18.7.3.1

Single Analog Input

When performing conversions at 600 ksps for a single

analog input, at least two sample and hold channels

must be enabled. The analog input multiplexer must be

configured so that the same input pin is connected to

both sample and hold channels. The A/D converts the

value held on one S/H channel, while the second S/H

channel acquires a new input sample.

18.7.3.2

Multiple Analog Input

The ADC can also be used to sample multiple analog

inputs using multiple sample and hold channels. In this

case, the total 600 ksps conversion rate is divided

among the different input signals. For example, four

inputs can be sampled at a rate of 150 ksps for each

signal or two inputs can be sampled at a rate of 300

ksps for each signal. Sequential sampling must be

used in this configuration to allow adequate sampling

time on each input.

12 x 1,000,000

= 83.33 ns

(12 + 2) X 750,000

= 95.24 ns

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